5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCST_PWRGD
H_PROCHOT_EC
Close to CPU
SKL_CNL_N:
FLOAT FOR SKL
GND FOR CNL
CFG7
PEG Training:
1: (Default) PEG Train immediately following RESET# de assertion.
0: PEG Wait for BIOS for training
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
PLACE UNDER CPU
Close to CPU
CFG High Low DESCRIPTION
No Stall Stall
Stall reset sequence after PCU
PLL lock until de-asserted
NORM Reversed PEG Static x16 Lane Numbering Reversal
Disable Enabled eDP enable
Disable Enabled PEG0CFGSEL[0]
Disable Enabled PEG0CFGSEL[1]
Reset# BIOS PEG_Defer_Training
Reserved configuration lane
~
0
1
2
3
4
5
6
7
8
19
CFG4
1: Disabled
0: Enabled
eDP Enable:
CFG2
1: Normal operation
0: Lane numbers reversed
PCI Express* Static x16 Lane Numbering Reversal
CLOSE TO CPU
L<1.1"
CFG6 CFG5 PEG CONFIG
0V 0V 1 x8, 2 x4 PEG
0V 1V RESERVED
1V 0V 2 x8 PEG
1V 1V 1 x16 PEG
PEG CONFIG TABLE
* All CFG 0 = Physical Strap Hi
* All CFG 1 = Physical Strap Lo
DIFF=85ohm, L=4"~9"
Zo=50ohm, L<15"
Zo=50ohm, L<12"
Zo=50ohm, L<11"
Zo=50ohm, L<12"
Zo=50ohm, L<10"
Zo=50ohm, L<6"
Zo=50ohm, L<15"
H_PROCHOT#H_PROCHOT_EC#AC_IN#
0 (keep 2 sec) to 1
001
0 (Idle keep 15m sec) to 1
VA
1 to 0
1
0=down freq to 800MHz
0 (Overlaod keep 2 sec) to 1 0 to 1
H_PROCHOT#
VCCST_PWRGD
SKL_CNL_N
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDO
H_TCK
CFG_RCOMP
VCCST_PWRGD
H_VIDALERT_N
H_PECI_R
CFG4
VCCST_PWRGD_R
H_PROCHOT#_RH_PROCHOT#
H_PM_DOWN_R
CFG5
CFG6
CFG7
CFG0
H_TDO
H_TCK
CFG2
1.05V_VCCSTVDD3
1.05V_VCCSTG
3.3VA
1.05V_VCCST
1.05V_VCCSTG
VDD3
1.05V_VCCSTG[7,36,63]
VDD3[10,28,32,33,34,35,36,39,41,42,45,54,55,56,57,59,60,61,62,63,64,65,67,69,70,71]
1.05V_VCCST[7,35,63,64]
3.3VA[32,33,35,36,39,41,43,59,61,62,63]
ALL_SYS_PWRGD[10,41,42,64]
PCH_CPU_BCLK_R_DN[38]
PCH_CPU_BCLK_R_DP[38]
PCH_CPU_PCIBCLK_R_DN[38]
PCH_CPU_PCIBCLK_R_DP[38]
CPU_24MHZ_R_DN[38]
CPU_24MHZ_R_DP[38]
H_PWRGD[36]
PLTRST_CPU#[35]
H_PM_SYNC[35]
H_TRST# [41]
H_PREQ# [41]
H_THERMTRIP#[35]
H_SKTOCC_N[37]
H_PRDY# [41]
H_TDO [36]
H_TDI [36]
H_TMS [36]
H_TCK [36]
H_PROCHOT#[64]
H_PM_DOWN[35]
H_CPU_SVIDCLK[64]
H_CPU_SVIDDAT[64]
H_CPU_SVIDALRT#[64]
H_PECI[42]
DDR_VTT_PG_CTRL[61]
H_PROCHOT#_EC[42]
AC_IN#[32,42,71]
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[04] CPU E/13 CLK,CFG,JTAG
A3
484Tuesday, March 10, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[04] CPU E/13 CLK,CFG,JTAG
A3
484Tuesday, March 10, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
Title
Size Document Number R e v
Date: Sheet
of
6-71-PB5D0-D02
D02
[04] CPU E/13 CLK,CFG,JTAG
A3
484Tuesday, March 10, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50DF2
R558 499_1%_04
S
D
G
Q52A
MTDK3S6R
2
61
R535 *short_04
C1349
*0.1u_6.3V_X5R_02
C1347
*0.1u_6.3V_X5R_02
R566 1K_04
R561 *51_04
R537 *short_04
R559 51_04
R126 1K_04
C1292 *0.1u_10V_X5R_04
R560
1K_04
D52 RB751S-40H
AC
R536 56.2_1%_04
5 OF 13
U41E
CFL_H_62_INT_IP_CRB_CFLH/BGA
VIDSOUT
BH29
DDR_VTT_CNTL
BT13
VCCST_PWRGD
H13
PM_SYNC
BM34
PM_DOWN
BP31
PECI
BT34
CFG_18
BN22
PROC_TCK
BR28
CFG_19
BP22
THERMTRIP#
J31
PROC_TDO
BT28
CFG_0
BN25
PROC_TRST#
BP30
CFG_1
BN27
PROC_SELECT#
BN1
ZVM#
AT13
SKTOCC#
BR33
CFG_2
BN26
CFG_RCOMP
BT25
CFG_3
BN28
PROC_PREQ#
BL30
CFG_4
BR20
CFG_10
BT23
RESET#
BP35
CFG_5
BM20
CLK24N
D31
PROCPWRGD
BT31
CFG_11
BT22
CFG_6
BT20
BPM#_0
BR27
VIDSCK
BH32
BCLKN
A32
PCI_BCLKN
C36
BPM#_1
BT27
CFG_7
BP20
CFG_12
BM19
CLK24P
E31
CFG_8
BR23
CFG_13
BR19
BPM#_2
BM31
BCLKP
B31
PCI_BCLKP
D35
BPM#_3
BT30
PROCHOT#
BR30
CFG_9
BR22
CFG_14
BP19
RSVD2
AY13
CFG_15
BT19
RSVD1
AU13
PROC_PRDY#
BP27
CFG_16
BP23
CATERR#
BM30
PROC_TDI
BL32
MSM#
AW13
PROC_TMS
BP28
CFG_17
BN23
VIDALERT#
BH31
R604 60.4_1%_04
R545 220_04
S
D
G
Q60A
MTDK3S6R
2
61
S
D
G
Q52B
MTDK3S6R
5
34
R569
200K_04
R557 20_1%_04
R600 *0_04
R542 100_04
S
D
G
Q60B
MTDK3S6R
5
34
R125
*short-p_04
R556 *100K_04
R614
100K_04
R563 49.9_1%_04
R599
1K_04
R555 *short_04
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