40 EmCORE-i612VLS/C400 User's Manual
DRAM Settings
The first chipset settings deal with CPU access to dynamic random access
memory (DRAM). The default timings have been carefully chosen and should
only be altered if data is being lost. Such a scenario might well occur if your
system had mixed speed DRAM chips installed so that greater delays may be
required to preserve the integrity of the data held in the slower memory
chips.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster performance; and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed in the system.
Chipset Features Setup
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