CY7C68013
Document #: 38-08012 Rev. *A Page 33 of 48
reserved
reserved
E6E2 1 EP6GPIFFLGSEL
[6]
Endpoint 6 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6E3 1 EP6GPIFPFSTOP Endpoint 6 GPIF stop trans-
action on prog. flag
0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW
E6E4 1 EP6GPIFTRIG
[6]
Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W
3 reserved
reserved
reserved
E6EA 1 EP8GPIFFLGSEL
[6]
Endpoint 8 GPIF Flag select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6EB 1 EP8GPIFPFSTOP Endpoint 8 GPIF stop trans-
action on prog. flag
0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW
E6E
C
1 EP8GPIFTRIG
[6]
Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W
3 reserved
E6F0 1 XGPIFSGLDATH GPIF Data H (16-bit mode
only)
D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
E6F1 1 XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transaction
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E6F2 1 XGPIFSGLDATL-
NOX
Read GPIF Data L, no trans-
action trigger
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
E6F3 1 GPIFREADYCFG Internal RDY, Sync/Async,
RDY pin states
INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr
E6F4 1 GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R
E6F5 1 GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W
E6F6 2 reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
2048 reserved RW
F000 1024 EP2FIFOBUF 512/1024-byte EP 2 / slave
FIFO buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO
buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F600 512 reserved
F800 1024 EP6FIFOBUF 512/1024-byte EP 6 / slave
FIFO buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FC00 512 EP8FIFOBUF 512 byte EP 8 / slave FIFO
buffer (IN or OUT)
D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FE00 512 reserved
xxxx I²C Compatible Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx
[8]
n/a
Special Function Registers (SFRs)
80 1 IOA
[7]
Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
81 1 SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW
82 1 DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
83 1 DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
84 1 DPL1
[7]
Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
85 1 DPH1
[7]
Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
86 1 DPS
[7]
Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW
87 1 PCON Power Control SMOD0 x 1 1 GF1 GF0 STOP IDLE 00110000 RW
88 1 TCON Timer/Counter Control (bit
addressable)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW
89 1 TMOD Timer/Counter Mode Control GATE CT M1 M0 GATE CT M1 M0 00000000 RW
8A 1 TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8B 1 TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8C 1 TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8D 1 TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8E 1 CKCON
[7]
Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW
8F 1 reserved
90 1 IOB
[7]
Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
91 1 EXIF
[7]
External Interrupt Flag(s) IE5 IE4 I²CINT USBNT 1 0 0 0 00001000 RW
92 1 MPAGE
[7]
Upper Addr Byte of MOVX
using @R0 / @R1
A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
93 5 reserved
98 1 SCON0 Serial Port 0 Control (bit ad-
dressable)
SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW
99 1 SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
Notes:
7. SFRs not part of the standard 8051 architecture.
8. If no EEPROM is detected by the SIE then the default is 00000000.
Table 5-1. FX2 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
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