Delta ASD-A2R-1B43 Series

Chapter 8 ParametersASDA-A2R Series
8-106 Revision December, 2014
Unit：
-
Range：
0 ~ 0x2
Data Size：
16bit
Format：
HEX
Settings：
Please refer to table 8.1 for digital input setting.
When set digital input (DI) as CCLR, the function of pulse clear is
effective. Clear the position error (It is applicable in PT, PR mode).
If this DI is ON, the accumulative position error will be cleared to
0.
0: The triggering method of CCLR is rising-edge.
1: The triggering method of CCLR is level.
P2-51 Reserved
Address: 0266H
0267H
P2-52 Reserved
Address: 0268H
0269H
P2-53 KPI Position Integral Compensation
Address: 026AH
026BH
Operational
Interface：
Panel / Software Communication
Related Section:
6.3.6
Default：
0
Control
Mode：
ALL
Unit：
rad/s
Range：
0 ~ 1023
Data Size：
16bit
Format：
DEC
Settings：
When increasing the value of position control integral, reducing
the position steady-state error, it may easily cause position
overshoot and noise if the value is set too big.
P2-54
SVP The Gain of Synchronous Speed Control
Address: 026CH
026DH
Operational
Interface：
Panel / Software Communication
Related Section: -
Default：
0
Control
Mode：
ALL
Unit：
Rad/s