Denon AVR-X1400H Service Manual

PCM5100PWR (DIGITAL_NETWORK : IC765)
Block diagram
PCM5100, PCM5101, PCM5102
SLAS764 – MAY 2011 www.ti.com
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510x
PCM510X (top view)
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
I/O DESCRIPTION
NAME NO.
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
DEMP 10 I De-emphasis control for 44.1kHz sampling rate
(1)
: Off (Low) / On (High)
FLT 11 I Filter select : Normal latency (Low) / Low latency (High)
SCK 12 I System clock input
BCK 13 I Audio data bit clock input
DIN 14 I Audio data input
LRCK 15 I Audio data word clock input
FMT 16 I Audio format selection : I
2
S (Low) / Left justified (High)
XSMT 17 I Soft mute control : Soft mute (Low) / soft un-mute (High)
LDOO 18 - Internal logic supply rail terminal for decoupling
DGND 19 - Digital ground
DVDD 20 - Digital power supply, 3.3V
(1) Failsafe LVCMOS Schmitt trigger input
6 Copyright © 2011, Texas Instruments Incorporated
Audio Interface
8x Interpolation Filter
32bit ∆Σ Modulator
Current
Segment
DAC
Current
Segment
DAC
I/V I/ V
Analog
Mute
Analog
Mute
Zero
Data
Detector
UVP/Reset
PLL Clock
Power
Supply
Ch. PumpPOR
Clock Halt
Detection
Advanced Mute Control
MCK
BCK
LRCK
CAPP
CAPM
VNEG
LINE OUT
DIN (i2s)
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
DVDD (3.3V)
GND
PCM5100, PCM5101, PCM5102
SLAS764 – MAY 2011 www.ti.com
Table 1. Differences Between PCM510x Devices
Part Number Dynamic Range SNR THD
PCM5102 112dB 112dB –93dB
PCM5101 106dB 106dB –92dB
PCM5100 100dB 100dB –90dB
spacer
Figure 1. PCM510x Functional Block Diagram
2 Copyright © 2011, Texas Instruments Incorporated
AD8195 (F-HDMI : IC811)
AD8195 Terminal Functions
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1IN0
2IP0
3IN1
4IP1
5VTTI
6IN2
7IP2
10AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40 SCL_IN 39 SDA_IN
38 CEC_IN 37 AVEE 36 VREF_IN
35 SCL_OUT 34 SDA_OUT
31 CEC_OUT
11ON0 12OP0
13VTTO 14ON1
15OP1
16AVCC
17ON2
20OP3
9IP3
8IN3
22 AVCC
23 AVCC
19ON3
18OP2
32 AMUXVCC 33 VREF_OUT
PIN 1
INDICATOR
Mnemonic
IN0
IP0
IN1
IP1
VTTI
IN2
IP2
IN3
IP3
AVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
COMP
AVEE
TX_EN
PE_EN
CEC_OUT
AMUXVCC
VREF_OUT
SDA_OUT
SCL_OUT
VREF_IN
CEC_IN
SDA_IN
SCL_IN
Type
1
HS I
HS I
HS I
HS I
Power
HS I
HS I
HS I
HS I
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Power
Control
Control
LS I/O
Power
Reference
LS I/O
LS I/O
Reference
LS I/O
LS I/O
LS I/O
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AV
CC.
High
Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Preemphasis Enable Parallel Interface.
CEC Output Side.
Positive Auxiliary Buffer Supply. 5 V nominal.
DDC Output Side Pull-Up Reference Voltage.
DDC Output Side Data Line Input/Output.
DDC Output Side Clock Line Input/Output.
DDC Input Side Pull-Up Reference Voltage.
CEC Input Side.
DDC Input Side Data Line.
DDC Input Side Clock Line
Pin No.
1
2
3
4
5
6
7
8
9
10, 16, 22, 23, 25, 26, 30
11
12
13
14
15
17
18
19
20
21
24,
27, 37,
Exposed Pad
28
29
31
32
33
34
35
36
38
39
40
1
HS = high speed, LS = low speed, I = input, and O = output.
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1IN0
2IP0
3IN1
4IP1
5VTTI
6IN2
7IP2
10AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40 SCL_IN 39 SDA_IN 38 CEC_IN 37 AVEE 36 VREF_IN 35 SCL_OUT 34 SDA_OUT 31 CEC_OUT
11ON0 12OP0 13VTTO 14ON1 15OP1 16AVCC 17ON2 20OP3
9IP3
8IN3
22 AVCC
23 AVCC
19ON3 18OP2
32 AMUXVCC 33 VREF_OUT
PIN 1
INDICATOR
Mnemonic
IN0
IP0
IN1
IP1
VTTI
IN2
IP2
IN3
IP3
AVCC
ON0
OP0
VTTO
ON1
OP1
ON2
OP2
ON3
OP3
COMP
AVEE
TX_EN
PE_EN
CEC_OUT
AMUXVCC
VREF_OUT
SDA_OUT
SCL_OUT
VREF_IN
CEC_IN
SDA_IN
SCL_IN
Type
1
HS I
HS I
HS I
HS I
Power
HS I
HS I
HS I
HS I
Power
HS O
HS O
Power
HS O
HS O
HS O
HS O
HS O
HS O
Control
Power
Control
Control
LS I/O
Power
Reference
LS I/O
LS I/O
Reference
LS I/O
LS I/O
LS I/O
Description
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Input Termination Supply. Nominally connected to AVCC.
High Speed Input Complement.
High Speed Input.
High Speed Input Complement.
High Speed Input.
Positive Analog Supply. 3.3 V nominal.
High Speed Output Complement.
High Speed Output.
Output Termination Supply. Nominally connected to AV
CC.
High
Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
High Speed Output Complement.
High Speed Output.
Power-On Compensation Pin. Bypass to ground through a 10 µF capacitor.
Negative Analog Supply. 0 V nominal.
High Speed Output Enable Parallel Interface.
High Speed Preemphasis Enable Parallel Interface.
CEC Output Side.
Positive Auxiliary Buffer Supply. 5 V nominal.
DDC Output Side Pull-Up Reference Voltage.
DDC Output Side Data Line Input/Output.
DDC Output Side Clock Line Input/Output.
DDC Input Side Pull-Up Reference Voltage.
CEC Input Side.
DDC Input Side Data Line.
DDC Input Side Clock Line
Pin No.
1
2
3
4
5
6
7
8
9
10, 16, 22, 23, 25, 26, 30
11
12
13
14
15
17
18
19
20
21
24,
27, 37,
Exposed Pad
28
29
31
32
33
34
35
36
38
39
40
1
HS = high speed, LS = low speed, I = input, and O = output.
54
Caution in
servicing
Electrical Mechanical Repair Information Updating

Denon AVR-X1400H Specifications

General

Receiver type	Surround
Frequency range	20 - 20000 Hz
Pre-out channels	2 SW
Input sensitivity	200 mV
Pre-out connectivity	Yes
Audio output channels	7.2 channels
Signal-to-Noise Ratio (SNR)	98 dB
Total Harmonic Distortion (THD)	0.08 %
Power output per channel (1KHz@6 Ohm)	145 W
Power output per channel (20-20KHz@8 Ohm)	80 W
HDMI in	6
Digital audio coaxial in	0
Ethernet LAN (RJ-45) ports	1
Multichannel audio input type	RCA
Component video (YPbPr/YCbCr) in	2
Headphone connectivity	3.5 mm
Connectivity technology	Wired & Wireless
Speakers connectivity type	3.5mm
Audio formats supported	ALAC, DSD, FLAC, MP3, WAV
Display	VFL
HDCP version	2.2
Apple docking	No
Product color	Black
Audio decoders	DTS-HD Master Audio, DTS:X, Dolby Atmos, Dolby Surround
Volume control	Rotary
Center speaker impedance	16 Ω
AM band range	522 - 1611 kHz
FM band range	87.5 - 108 MHz
Supported radio bands	AM, FM
Internet radio services supported	Deezer, Napster, Pandora, SIRIUS Internet Radio, Spotify, Tidal, iHeartRadio
AC input voltage	230 V
AC input frequency	50 Hz
Power consumption (standby)	0.1 W
Power consumption (typical)	430 W
Supported video modes	720i, 720p, 960p, 1080i, 1080p, 2160p
Supported graphics resolutions	3840 x 2160
Certification	CE, EAC

Weight and Dimensions

Depth	339 mm
Width	434 mm
Height	151 mm
Weight	8500 g