Denon AVR-X2000 Service Manual

A3V56S30FTP-G6 (HDMI:U2604,2605)
A3V56S30FTP-G6 Pin Function
A3V56S30FTP A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Revision 1.1 Mar., 2010
Page 2 / 39
CLK : Master Clock DQM : Output Disable / Write Mask (A3V56S30FTP)
CKE : Clock Enable DQMU,L : Output Disable / Write Mask (A3V56S40FTP) /CS : Chip Select A0-12 : Address Input
/RAS : Row Address Strobe BA0,1 : Bank Address /CAS : Column Address Strobe Vdd : Power Supply /WE : Write Enable VddQ : Power Supply for Output DQ0-7 : Data I/O (A3V56S30FTP) Vss : Ground DQ0-15 : Data I/O (A3V56S40FTP) VssQ : Ground for Output
BA0 BA1
Vdd DQ0 VddQ
DQ1 DQ2 VssQ
DQ3 DQ4 VddQ
DQ5 DQ6 VssQ
DQ7 Vdd DQML
/WE /CAS /RAS /CS
A
10(AP)
A
2
A
3
Vdd
A
0
A
1
Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1
A
10(AP)
A
2
A
3
Vdd
A
0
A
1
DQM CKE
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE
A
12
A
11
A
8
A
7
A
6
A
5
A
4
Vss
A
9
Vss DQ7
VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC CLK
A
12
A
11
A
8
A
7
A
6
A
5
A
4
Vss
A
9
PIN CONFIGURATION (TOP VIEW)
PIN CONFIGURATION
(TOP VIEW)
x8
x16
1 2 3 4 5 6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
23 32 24 31 25 30 26 29 27 28
A3V56S30FTP
A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Revision 1.1 Mar., 2010
Page 4 / 39
Pin Descriptions
SYMBOL TYPE DESCRIPTION
CLK Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst /
access in progress). CKE is synchronous except after the device enters self refresh mode, where
CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH.
/CS Input
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
/CAS,
/RAS,
/WE
Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
DQM,
DQML,
DQMU,
Input
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output disable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM
corresponds to DQ0–DQ7 (A3V56S30FTP). DQML corresponds to DQ0–DQ7, DQMU
corresponds to DQ8–DQ15 (A3V56S40FTP).
BA0, BA1 Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
A0–A12 Input
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is
specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also
used to indicate precharge option. When A10 is high at a read / write command, an auto
precharge is performed. When A10 is high at a precharge command, all banks are precharged.
DQ0–DQ15 I/O
Data Input / Output: Data bus.
NC –
Internally Not Connected: These could be left unconnected, but it is recommended they be
connected or V
SS.
VddQ Supply
Data Output Power: Provide isolated power to output buffers for improved noise immunity.
VssQ Supply
Data Output Ground: Provide isolated ground to output buffers for improved noise immunity.
Vdd Supply
Power for the input buffers and core logic.
Vss Supply
Ground for the input buffers and core logic.
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS /RAS
/CS
BA0 BA1
A10(AP)
A0 A1 A2 A3
Vdd
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
165

Denon AVR-X2000 Specifications

General

Receiver type	-
Frequency range	10 - 100000 Hz
Output impedance	16 Ω
Input sensitivity	200 mV
Audio output channels	7.1 channels
Signal-to-Noise Ratio (SNR)	100 dB
Power output per channel (1KHz@6 Ohm)	125 W
Power output per channel (20-20KHz@8 Ohm)	95 W
HDMI in	7
AC (power) in	Yes
Audio (L/R) in	4
Composite video in	2
Component video (YPbPr/YCbCr) in	1
Connectivity technology	Wired
Speakers connectivity type	Banana connector
Audio formats supported	AAC, FLAC, MP3, WAV, WMA
Image formats supported	JPG
Wi-Fi	No
RDS features	PTY, TP
FM band range	87.5 - 108 MHz
Supported radio bands	FM
Internet radio services supported	Spotify, vTuner
Supported video modes	1080i, 1080p, 480p, 576p, 720p
Display	VFL
Color depth	24 bit
Aspect ratio	4:3, 16:9
Product color	Black
Audio decoders	Dolby Digital, Dolby Digital EX, Dolby Digital Plus, Dolby Pro Logic IIx, Dolby Pro Logic IIz, Dolby TrueHD, DTS, DTS-ES, DTS-HD, DTS-HD Master Audio
USB 2.0 ports quantity	USB 2.0 ports have a data transmission speed of 480 Mbps, and are backwards compatible with USB 1.1 ports. You can connect all kinds of peripheral devices to them.
Apple docking compatibility	Not supported
AC input voltage	230 V
AC input frequency	50 - 60 Hz
Power consumption (standby)	0.1 W
Power consumption (typical)	500 W

Weight and Dimensions

Depth	330 mm
Width	434 mm
Height	167 mm
Weight	9500 g