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FIBOCOM L850-GL Series Hardware Guide Page 18 of 59
Pin Pin Name I/O Reset Value Pin Description Type
46 SYSCLK O PD 26M clock output 1.8V
47 PERn0 I
-
PCIe RX differential signal
Negative
-
48 TX_BLANKING O PD
PA blanking timer,
Reserved
1.8V
49 PERp0 I
-
PCIe RX differential signal
Positive
-
50 PERST# I PU
Asserted to reset module PCIe interface
default. If module went into core dump,
it will reset whole module, not only PCIe
interface.
Active low, internal pull up(10KΩ)
3.3V
51 GND
- -
GND Power Supply
52 CLKREQ# I/O PU
Asserted by device to request a PCIe
reference clock be available (active
clock state) in order to transmit data. It
also used by L1 PM Sub states
mechanism, asserted by either host or
device to initiate an L1 exit.
Active low, internal pull up(10KΩ)
3.3V
53 REFCLKN I
-
PCIe reference clock signal,
Negative
-
54 PEWAKE# O L
Asserted to wake up system and
reactivate PCIe link from L2 to L0, it
depends on system
whether supports wake up functionality.
Active low, open drain output and
should add external pull up(100KΩ) on
platform
3.3V
55 REFCLKP I
-
PCIe reference clock signal,
Positive
-
56 RFFE_SCLK O
-
MIPI interface tunable ANT,
RFFE clock
1.8V
57 GND
- -
GND Power Supply
58 RFFE_SDATA O
-
MIPI interface tunable ANT,
RFFE data
1.8V
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