Furuno FAR-2807 Series - Page 351

7.2 Antenna Unit
7-7
Fig. 7.2.2 Block Diagram of RFC board
U15
U15
RF RX
RF TX
RF RX data
RF TX data
HD
BP
HD
BP
STC DETECT
TX-HV PRTECT
STC-CONT
Q1, Q5, Q6
Q2, Q7, Q8
Q3, Q9, Q10
Q4, Q11, Q12
TRIG 1
V TRIG
TRIG 2
TRIG 3
TRIG 4
TUNE
TUNE SYNC
TUNE SCLK
TUNE DIN
STC ATT(NC)
ISTC ATT
SDATA/CLK/DATAE
VBW A/B
TUNE GAIN
PIN ATT CONT
FET ATT
TUNE GATE
SAMPL HOLD
MSB ENABLE
TEST SIG ENABL
PIN ATT CONT
FET ATT
TUNE GATE
SAMPL HOLD
MSB ENABLE
TEST SIG ENABL
D MONI AD
N12V N12V AD
TUNE AD
D MONI
TUNE
TUNE IND
INT BP/INT HD CLK 16MHz
U25
U6
CLOCK
TEST SIG
INT TRG INT UART RX INT UART TX
Vcc INT
3.3V
U4/U5
2P5(2.5V)
3.3V
JP3 -J P5
BVER 0-3
U29
(Reset)
U30
Reset
FPGA Reset
TEMP OUT
PROTECT AD
U20
(TEMP. DET)
2.5V
U12
PM LEVL
PM LEVL
U12
U11
HEATER VLT
HEATER OFF
HEATER VLT
HEATER OFF
HEATER AD
HEATER
HEATER
P12V AD
P5V AD
P32V AD
N12V AD
P12V
P5V
P32V
N12V
U3
U13
(D/A)
CS/WR/RD
U28
(Flash ROM)
U27
(RAM)
U26
(EEPROM)
Data D0-7
Data D0-7
ADD. AD1-19
U16
(D/A)
2.5V
2.5V
U23
PM Trig
PM Trig
U23
PM Enable
PM Enable
U10
U19
(RFC CPU)
U17
(FPGA)
U22
U14
U14
U30
U30
TX HV INHBI
M3 - L
S - M2
MAG-CUR-IN
TUNE SYNC
TUNE SCLK
TUNE DIN
U24
MAG CUR LVL
2.5V
U8
TUNING BIAS
U18
(D/A)
U5
U5
2.5V
Data D0-7
U7
(A/D)
MD
(03P9244)
IF
(03P9335)
IF
(03P9335)
PWR(RF)
(03P9348)
U12, 1
SPU
96MHz
BP GEN
(03P9347)
PM
SHORT
SHORT
TX SIG
BUZ OUT
CR9 (CPU RUN)
U3
U3/21
Q13
U21
Motor ON
+12V
TB
(03P9349)
J917
J917
TB803
Rer. VOL
RFC (03P9346A)
M30620FCNFP
XC2100E-6TQ144I
RPU-013
MAG DETECT