Giga-tronics 80350A - Page 8

Series 8035XA Peak Power Sensors
iv Manual 21568, Rev. F March 2008
Illustrations
Figure 2-1: Sensor Setup Menu Tree ......................................................................2-2
Figure 2-2: Internal Triggering Levels......................................................................2-3
Figure 2-3: 8035XA Sensor Timing Diagram...........................................................2-4
Figure 2-4: Sample Delay Adjustment Display ........................................................2-6
Figure 2-5: Channel A Default Sample Delay ..........................................................2-7
Figure 2-6: Channel B Default Sample Delay...........................................................2-7
Figure 2-7: Channel A & B Default Sample Delay....................................................2-7
Figure 2-8: Sample Delay with Uncalibrated Sensor ...............................................2-7
Figure 2-9: Sample Delay with No Trigger Display..................................................2-9
Figure 2-10: Sample Dely Over-Range Indication......................................................2-9
Figure 2-11: Sample Delay Over-Range Offset Display............................................2-10
Figure 2-12: Pulse Profile and Sample Delay Test Setup.........................................2-11
Figure 2-13: Sample Delay......................................................................................2-12
Figure 2-14: Using SD to Offset a 0 ns Time Reference...........................................2-12
Figure 2-15: SD Setting for Measuring Pulse Droop................................................2-13
Figure 2-16: Using SD to Measure a 3 dB Pulse Width...........................................2-14
Figure 3-1: 8035XA High Level Block Diagram........................................................3-2
Figure 3-2: Analog PC Assembly Block Diagram.....................................................3-3
Figure 3-3: Analog Circuit Timing Diagram.............................................................3-4
Figure 3-4: Digital PC Assembly Block Diagram......................................................3-5
Figure 3-5: Digital Timing Diagram, INT/EXT Trig Mode..........................................3-7
Figure 3-6: Digital Timing Diagram, CW Mode .......................................................3-8
Figure 3-7: Digital Serial Data Cycle Timing Diagram..............................................3-8
Figure 4-8: Power Linearity Test Setup...................................................................4-2
Figure 4-9: Detector Output and Trigger Level Setup..............................................4-4
Figure 5-10: Principal Test Component Locations.....................................................5-2