GOWIN UART Master IP - 3 Signal Definition; Gowin UART Master IP; SRAM Interface Signal; UART Side Signal

3Signal Definition
3.1Gowin UART Master IP
IPUG511-1.4E
4(15)
3Signal Definition
3.1 Gowin UART Master IP
3.1.1 SRAM Interface Signal
Table3-1 SRAM Interface Signal Definition
No.
Signal name
I/O
Description
Remarks
1
I_CLK
I
Working clock, rising edge
sampling
-
2
I_RESETN
I
Reset signal
-
3
I_TX_EN
I
Write enable signal
SRAM write
address
channel signal
4
I_WADDR
I
Write data signal
5
I_WDATA
O
Write address preparation
6
I_RX_EN
I
Read enable signal
RSAM read
address
channel signal
7
I_RADDR
I
Read address signal
8
O_RDATA
O
Read data signal
3.1.2 UART Side Signal
Table3-2 UART Side Signal Definition
No.
Signal name
I/O
Description
Remarks
1
SIN
I
Serial data input
-
2
RxRDYn
O
Ready to receive
-
3
SOUT
O
Serial data output
-
4
TxRDYn
O
Ready to send
-
5
DDIS
O
Disable driver
-
6
INTR
O
Interrupt signal
-
7
DCDn
I
Data carrier detection, low
effective
Modem
interface
8
CTSn
I
Run send, low effective
9
DSRn
I
Data communication
equipment is ready, low
effective
10
RIn
I
Ringing prompt, low effective
11
DTRn
O
Data terminal is ready, low
effective