GOWIN UART Master IP - Interrupt Identification Register (IIR); Figure 4-4 Interrupt Enable Register; Figure 4-5 Interrupt Identification Register; Table4-4 Interrupt Enable Register Bit Definition

4Working Principle
4.2Gowin UART Master IP Register
IPUG511-1.4E
8(15)
Figure4-4 Interrupt Enable Register
31 8
7 4
3
2
1
0
Reserved
0000
MSI
RLSI
THRI
RHRI
Table4-4 Interrupt Enable Register Bit Definition
Bit
Name
Defaults
Access type
Description
31 4
Reserved
N/A
N/A
Reserved
3
MSI
0x0
write
Modem status interrupt enable
 0：Disable Modem status
interrupt
 1：Enable Modem status
interrupt
2
RLSI
0x0
write
Receive line status interrupt
enable
 0：Disable receive line status
interrupt
 1：Enable Receive Line
Status Interrupt
1
THRI
0x0
write
Transmit Holding Register Empty
Interrupt Enable
 0：Disable transmit hold
register empty interrupt
 1：Enable transmit hold
register empty interrupt
0
RBRI
0x0
write
Receive data valid interrupt
enable
 0：Disable receive data valid
interrupt
 1：Enable receive data valid
interrupt
4.2.4 Interrupt Identification Register (IIR)
The interrupt identification register is shown in Figure4-5. The interrupt
identifier register contains the priority of the interrupt identifier. The bit definition
is shown in Table4-5.
Figure4-5 Interrupt Identification Register
31 8
7 4
3
2
1
0
Reserved
0000
INT2
INT1
INT0
INT STAT
Table4-5 Interrupt Identification Register Bit Definition
Bit
Name
Defaults
Access type
Description
31:4
Reserved
N/A
N/A
Reserved
3
INT2
0x0
read
FIFO enable
 0:16450 mode
 1:16550 mode
2
INT1
0x0
read
Interrupt identifier
 11：Receive line status (highest
priority)
 10：Receive data available (Level
2)
 01：Send Hold Register Empty
(Level 3)
 00：Modem status (Level 4)
1
INT0
0
INT STAT
0x1
read
0： Interrupt waiting