GOWIN UART Master IP - Receive Buffer Register (RBR); Transmit Holding Register (THR); Interrupt Enable Register (IER); Figure4-2 Receive Buffer Register

4Working Principle
4.2Gowin UART Master IP Register
IPUG511-1.4E
7(15)
Table4-1 Gowin UART Master IP Register
Register name
Register address
Register bit width
Types
Description
RBR
0x00
8
read
Receive Buffer
Register
THR
0x00
8
write
Transmit Holding
Register
IER
0x01
8
write
Interrupt Enable
Register
IIR
0x02
8
read
Interrupt
Identification
Register
LCR
0x03
7
write
Line Control
Register
MCR
0x04
8
write
Modem Control
Register
LSR
0x05
7
read
Line State
Register
MSR
0x06
8
read
Modem Status
Register
4.2.1 Receive Buffer Register (RBR)
The receive buffer register is shown in Figure4-2. The specific bit definition
of the register is shown in Table4-2.
Figure4-2 Receive Buffer Register
31 8
7 0
Reserved
RBR
Table4-2 Receive Buffer Register Bit Definition
Bit
Name
Defaults
Access type
Description
31:8
Reserved
N/A
N/A
Reserved
7:0
RBR
0x0
read
Cache the last
received byte
4.2.2 Transmit Holding Register (THR)
The transmit holding register is shown in Figure4-3. The transmit
holding register contains the data to be sent next time. The specific bit
definitions are shown in Table4-3.
Figure4-3 Transmit Holding Register
31 8
7 0
Reserved
THR
Table4-3 Transmit Holding Register Bit Definitions
Bit
Name
Defaults
Access type
Description
31:8
Reserved
N/A
N/A
Reserved
7:0
THR
0x0
write
Keep the last sent byte
4.2.3 Interrupt Enable Register (IER)
The interrupt enable register is shown in Figure4-4. The interrupt
enable register contains the bits that make the interrupt valid. The bit
definition is shown in Table4-4.