(Preliminary) M12L16161A (2Q)
Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2011
Revision : 0.1 1/28
SDRAM 512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
z JEDEC standard 3.3V power supply
z LVTTL compatible with multiplexed address
z Dual banks operation
z MRS cycle with address key programs
- CAS Latency (2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
z All inputs are sampled at the positive going edge of the
system clock
z Burst Read Single-bit Write operation
z DQM for masking
z Auto & self refresh
z 32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID Max Freq. Package Comments
M12L16161A-5TG2Q
200MHz
TSOP(II) Pb-free
M12L16161A-7TG2Q
143MHz
TSOP(II) Pb-free
PIN CONFIGURATION (TOP VIEW)
(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch )
VDD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Harman Kardon
VR 151 Service Manual
Page 105 of 131
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