I/O Port Control Registers
Each I/O line has its own control register (PAC, PBC, PCC, etc.,) to control the input/output configu
-
ration. With this control register, each CMOS output or Schmitt Trigger input with or without
pull-high resistor structures can be reconfigured dynamically under software control. Each pin of
the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to func
-
tion as an input, the corresponding bit of the control register must be written as a ²1². This will then
allow the logic state of the input pin to be directly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is cur
-
rently setup as an output, instructions can still be used to read the output register. However, it
should be noted that the program will in fact only read the status of the output data latch and not
the actual logic status of the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but
by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins,
the chosen function of the multi-function I/O pins is set by configuration options while for others the
function is set by application program control.
Buzzer
The buzzer pins BZ and BZ
are pin-shared with I/O pins PB0 and PB1. If configured as buzzer
pins, the correct hardware and software options must be selected.
External Interrupt Input
The external interrupt pin INT
is pin-shared with the I/O pin PC0 or PG0 depending upon which de-
vice is used. However, for the HT48R70A-1/HT48C70-1 devices, the external interrupt pin INT
is
an independent non shared pin. For the HT48RU80/HT48CU80 devices only, there are two exter-
nal interrupt pins, the INT0
pin, which exists as an independent pin and the INT1 pin which is
pin-shared with the I/O pin PB2. For these pins to operate as external interrupt pins and not as a
normal I/O pin, the corresponding external interrupt enable bits in the INTC, INTC0 and INTC1 in-
terrupt control registers must be correctly set. For applications not requiring an external interrupt
input, the pin-shared external interrupt pins can be used as normal I/O pins, however to do this,
the external interrupt enable bits in the INTC register must be disabled.
External Timer Clock Input
Each device contains either one or two timers depending upon which one is chosen. Each timer
has an external input pin, which in the case of devices with a single timer, is known as TMR and in
the case of devices with two timers are known as TMR0 and TMR1. For all devices with a single
timer, the external input pin TMR is pin-shared with I/O pin PC0 or PC1. For devices with two tim
-
ers, the external input pins TMR0 and TMR1 are pin-shared with pins PC0 and PC5 respectively
or exist as independent non-shared pins depending upon which device and which package is se
-
lected. The HT48RU80/HT48CU80 devices contain three timers, all of which have external timer
pins, TMR0, TMR1 and TMR2. The TMR0 and TMR1 pins are independent pins while the TMR2
pin is pin-shared with I/O pin PB3. These external timer pins, if they are shared pins, can be used
as normal I/O pins for applications that do not require external timer inputs. For such applications
the timer mode control bits in the timer control register must select the timer mode which has an
internal clock source, to prevent the I/O from interfering with the timer counter operation.
Chapter 1 Hardware Structure
37
To Next Page
Loading...
Need help?
General
