Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed time intervals, providing an internal inter
-
rupt signal each time the counter overflows. To operate in this mode, the bit pair, TM1/TM0,
T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, depending upon which timer is used, must be set to 1
and 0 respectively. In this mode the internal clock is used as the timer clock. Note that for the 8-bit
timers which are the single Timer/Event Counters in the HT48R10A-1/HT48C10-1 and
HT48R30A-1/HT48C30-1 devices, Timer/Event Counter 0 in the HT48R50A-1/HT48C50-1, and
Timer/Event Counter 2 in the HT48RU80/HT48CU80 devices, the timer input clock source is ei
-
ther f
SYS
or the f
RTC
. However, this timer clock source is further divided by a prescaler, the value of
which is determined by the bits PSC2~PSC0, T0PSC2~T0PSC0 or T2PSC2~T2PSC0 in the rele
-
vant Timer Control Register. For the remaining Timer/Event Counters, which are the 16-bit
Timer/Event Counters, the input clock frequency is f
SYS
/4 or the f
RTC
. There is no prescaler function
for the 16-bit timers. The timer-on bit, TON, T0ON, T1ON or T2ON, depending upon which timer is
used, must be set high to enable the timer to run. Each time an internal clock high to low transition
occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is gen
-
erated and the timer will preload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up
sources, however, the internal interrupts can be disabled by ensuring that the ETI or ET0I and
ET1I or ET2I bits of the INTC, INTC0 and INTC1 registers are reset to zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer pin, can
be recorded by the internal timer. For the timer to operate in the event counting mode, the bit pair,
TM1/TM0, T0M1/T0M0, T1M1/T1M0 or T2M1/T2M0, depending upon which timer is used, must
be set to 0 and 1 respectively. The timer-on bit, TON, T0ON, T1ON or T2ON, depending upon
which timer is used, must be set high to enable the timer to count. Depending upon which counter
is used, if TE, T0E, T1E or T2E is low, the counter will increment each time the external timer pin re
-
ceives a low to high transition. If TE, T0E, T1E or T2E is high, the counter will increment each time
the external timer pin receives a high to low transition. As in the case of the other two modes, when
the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will
then preload the value already loaded into the preload register. If the external timer pins are
pin-shared with other I/O pins, to ensure that the pin is configured to operate as an event counter
input pin, two things have to happen. The first is to ensure that the TM1/TM0, T0M1/T0M0,
T1M1/T1M0 or T2M1/T2M0 bits place the Timer/Event Counter in the event counting mode, the
second is to ensure that the port control register configures the pin as an input. It should be noted
that a timer overflow is one of the interrupt and wake-up sources.
Chapter 1 Hardware Structure
47
I n c r e m e n t
T i m e r C o n t r o l l e r
T i m e r C l o c k o r
P r e s c a l e r O u t p u t
T i m e r + 1 T i m e r + 2
T i m e r + N T i m e r + N + 1
Timer Mode Timing Chart
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