pin-shared with PG0. For the HT48RU80/HT48CU80 devices, the external interrupt pin INT1 is
pin-shared with PB2. Note that the external interrupt pins must be setup as inputs to enable cor
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rect operation.
Timer/Event Counter Interrupt
For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit
must be first set. For devices with a single timer, this is bit 2 of the INTC register and is known as
ETI. For devices with two timers, the Timer/Event Counter 0 interrupt enable is bit 2 of the INTC
register and known as ET0I while the Timer 1 interrupt enable is bit 3 of the INTC register and
known as ET1I. In the case of the HT48RU80/HT48CU80 devices, which have three internal
Timer/Event Counters, the Timer/Event Counter 0 interrupt enable is bit 2 of the INTC0 register
and known as ET0I, the Timer/Event Counter 1 interrupt enable is bit 3 of the INTC0 register and
known as ET1I and the Timer/Event Counter 2 interrupt enable is bit 2 of the INTC1 register and is
known as ET2I. An actual Timer/Event Counter interrupt will be initialized when the Timer/Event
Counter interrupt request flag is set, caused by a timer overflow. For devices which have a single
timer, this is bit 5 of the INTC register and is known as TF. For devices which have two timers, the
Timer/Event Counter 0 request flag is bit 5 of the INTC register and known as T0F, while the
Timer/Event Counter 1 request flag is bit 6 of the INTC register and known as T1F. In the case of
the HT48RU80/HT48CU80 devices, which has three timers, the Timer/Event Counter 0 request
flag is bit 5 of the INTC0 register and known as T0F, the Timer/Event Counter 1 request flag is bit 6
of the INTC0 register and known as T1F, and the Timer/Event Counter 2 request flag is bit 6 of the
INTC1 register and is known as T2F.
When the master interrupt global enable bit is set, the stack is not full and the corresponding timer
interrupt enable bit is set, an internal interrupt will be generated when the corresponding timer
overflows. This will create a subroutine call to location 08H for devices with a single timer. For de-
vices with two timers, a subroutine call to location 08H will occur for Timer/Event Counter 0 and a
subroutine call to location 0CH for Timer/Event Counter 1. For the HT48RU80/HT48CU80 de-
vices, which have three internal Timer/Event Counters, a subroutine call to location 08H will occur
for Timer/Event Counter 0, a subroutine call to location 0CH for Timer/Event Counter 1 and a sub-
routine call to location 018H for Timer/Event Counter 2. After entering the timer interrupt execution
routine, the corresponding timer interrupt request flag, either, TF, T0F, T1F or T2F will be reset and
the EMI bit will be cleared to disable other interrupts.
UART Interrupt
In the HT48RU80/HT48CU80 devices, which are the only devices which contain an internal UART
function, its corresponding UART interrupt is enabled by setting the EURI bit, which is bit 1 of the
INTC1 register. An actual UART interrupt will be initialized when the UART interrupt request flag
URF is set, which is bit 5 of the INTC1 register. When the master interrupt global bit is set, the
stack is not full and the corresponding EURI interrupt enable bit is set, a UART internal interrupt
will be generated when a UART interrupt request occurs. This will create a subroutine call to its cor
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responding vector location 014H. When a UART internal interrupt occurs, the interrupt request
flag URF will be reset and the EMI bit cleared to disable other interrupts.
There are various UART conditions, which can generate a UART interrupt, such as certain data
transmission and reception conditions, overrun errors as well as an address detect condition.
These conditions are reflected by various flags within the UART¢s status register, known as the
Chapter 1 Hardware Structure
57
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