Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of si
-
multaneous requests, the following table shows the priority that is applied.
Interrupt Source
HT48R10A-1
HT48C10-1
Priority
HT48R30A-1
HT48C30-1
Priority
HT48R50A-1
HT48C50-1
Priority
HT48R70A-1
HT48C70-1
Priority
HT48RU80
HT48CU80
Priority
External Interrupt 0 11111
Timer/Event Counter or
Timer/Event Counter 0 Overflow
22222
Timer/Event Counter 1 Overflow N/A N/A 3 3 3
External Interrupt 1 N/A N/A N/A N/A 4
UART Interrupt N/A N/A N/A N/A 5
Timer/Event Counter 2 Overflow N/A N/A N/A N/A 6
Note 1. For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices, there is only one
timer. The HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1 devices have two internal
timers, and the HT48RU80/HT48CU80 devices have three internal timers.
2. Only the HT48RU80/HT48CU80 devices have a UART interrupt.
In cases where several interrupts are enabled, and where more than one interrupt occur simulta
-
neously, the interrupt that is serviced first will follow the order shown in the table. Suitable masking
of the individual interrupts using the INTC or the INTC0 and INTC1 registers can prevent simulta
-
neous occurrences.
External Interrupt
For an external interrupt to occur, the corresponding external interrupt enable bit must be first set.
With the exception of the HT48RU80/HT48CU80 devices, that is for devices with a single external
interrupt pin, the enable bit is bit 1 of the INTC register, known as EEI. For the HT48RU80/
HT48CU80 devices, which have two external interrupt pins, the enable bit for pin INT0
is bit 1 of
the INTC0 register, known as EEI0, and bit 0 of the INTC1 register, known as EEI1, for pin INT1
.
An external interrupt is triggered by a high to low transition on the external interrupt pin, after which
the related interrupt request flag will be set. With the exception of the HT48RU80/HT48CU80 de
-
vices, that is for devices with a single external interrupt pin, this is bit 4 of the INTC register, known
as EIF. For the HT48RU80/HT48CU80 devices, there are two corresponding external interrupt re
-
quest flags, these are bit 4 of the INTC0 register, known as EIF0 and bit 4 of the INTC1 register,
known as EIF1. When the master interrupt and external interrupt bits are enabled, the stack is not
full and a high to low transition occurs on the external interrupt pin, a subroutine call to the corre
-
sponding external interrupt vector will occur. After entering the interrupt execution routine, the cor
-
responding interrupt request flag, either EIF, EIF0 or EIF1 will be reset and the EMI bit will be
cleared to disable other interrupts.
For the HT48R10A-1/HT48C10-1, the external interrupt pin INT
is pin-shared with PC0 and for the
HT48R30A-1/HT48C30-1 and HT48R50A-1/HT48C50-1 devices, the external interrupt pin INT
is
56
I/O Type MCU
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