Intel 8XC251SA - Page 112

8XC251SA, SB, SP, SQ USER’S MANUAL
6-8
Figure 6-3. Interrupt Priority High Register
Figure 6-4. Interrupt Priority Low Register
IPH0
Address: S:B7H
Reset State: X000 0000B
7 0
— IPH0.6 IPH0.5 IPH0.4 IPH0.3 IPH0.2 IPH0.1 IPH0.0
Bit
Number
Bit
Mnemonic
Function
7 — Reserved. The value read from this bit is indeterminate. Write a “0” to
this bit.
6 IPH0.6 PCA Interrupt Priority Bit High
5 IPH0.5 Timer 2 Overflow Interrupt Priority Bit High
4 IPH0.4 Serial I/O Port Interrupt Priority Bit High
3 IPH0.3 Timer 1 Overflow Interrupt Priority Bit High
2 IPH0.2 External Interrupt 1 Priority Bit High
1 IPH0.1 Timer 0 Overflow Interrupt Priority Bit High
0 IPH0.0 External Interrupt 0 Priority Bit High
IPL0
Address: S:B8H
Reset State: X000 0000B
7 0
— IPL0.6 IPL0.5 IPL0.4 IPL0.3 IPL0.2 IPL0.1 IPL0.0
Bit
Number
Bit
Mnemonic
Function
7 — Reserved. The value read from this bit is indeterminate. Write a “0” to
this bit.
6 IPL0.6 PCA Interrupt Priority Bit Low
5 IPL0.5 Timer 2 Overflow Interrupt Priority Bit Low
4 IPL0.4 Serial I/O Port Interrupt Priority Bit Low
3 IPL0.3 Timer 1 Overflow Interrupt Priority Bit Low
2 IPL0.2 External Interrupt 1 Priority Bit Low
1 IPL0.1 Timer 0 Overflow Interrupt Priority Bit Low
0 IPL0.0 External Interrupt 0 Priority Bit Low