Intel 8XC251SA - Default Chapter; Table of Contents

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CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.3 RELATED DOCUMENTS.............................................................................................. 1-5
1.3.1 Data Sheet ................................................................................................................1-6
1.3.2 Application Notes ......................................................................................................1-6
1.4 APPLICATION SUPPORT SERVICES.......................................................................... 1-7
1.4.1 World Wide Web .......................................................................................................1-7
1.4.2 CompuServe Forums ................................................................................................1-7
1.4.3 FaxBack Service .......................................................................................................1-8
1.4.4 Bulletin Board System (BBS) ....................................................................................1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 8XC251SA, SB, SP, SQ ARCHITECTURE ................................................................... 2-3
2.2 MCS 251 MICROCONTROLLER CORE....................................................................... 2-4
2.2.1 CPU ..........................................................................................................................2-5
2.2.2 Clock and Reset Unit ................................................................................................2-6
2.2.3 Interrupt Handler .......................................................................................................2-7
2.2.4 On-chip Code Memory ..............................................................................................2-7
2.2.5 On-chip RAM ............................................................................................................2-7
2.3 ON-CHIP PERIPHERALS.............................................................................................. 2-7
2.3.1 Timer/Counters and Watchdog Timer .......................................................................2-7
2.3.2 Programmable Counter Array (PCA) ........................................................................2-8
2.3.3 Serial I/O Port ...........................................................................................................2-8
CHAPTER 3
ADDRESS SPACES
3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS................................... 3-1
3.1.1 Compatibility with the MCS® 51 Architecture ...........................................................3-2
3.2 8XC251SA, SB, SP, SQ MEMORY SPACE.................................................................. 3-5
3.2.1 On-chip General-purpose Data RAM ........................................................................3-8
3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ) .............3-8
3.2.2.1 Accessing On-chip Code Memory in Region 00: ..................................................3-9
3.2.3 External Memory .....................................................................................................3-10
3.3 8XC251SA, SB, SP, SQ REGISTER FILE .................................................................. 3-10
3.3.1 Byte, Word, and Dword Registers ...........................................................................3-13
3.3.2 Dedicated Registers ................................................................................................3-13
3.3.2.1 Accumulator and B Register ..............................................................................3-13
3.3.2.2 Extended Data Pointer, DPX ..............................................................................3-15