Intel 8XC251SA - Page 12

8XC251SA, SB, SP, SQ USER’S MANUAL
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FIGURES
Figure Page
2-1 Functional Block Diagram of the 8XC251SA, SB, SP, SQ...........................................2-2
2-2 The CPU.......................................................................................................................2-5
2-3 Clocking Definitions......................................................................................................2-6
3-1 Address Spaces for MCS® 251 Microcontrollers .........................................................3-1
3-2 Address Spaces for the MCS® 51 Architecture ...........................................................3-3
3-3 Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture.............3-4
3-4 8XC251SA, SB, SP, SQ Address Space .....................................................................3-6
3-5 Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space .................3-7
3-6 The Register File........................................................................................................3-11
3-7 Register File Locations 0–7........................................................................................3-12
3-8 Dedicated Registers in the Register File and their Corresponding SFRs...................3-14
4-1 Configuration Array (On-chip).......................................................................................4-2
4-2 Configuration Array (External)......................................................................................4-3
4-3 Configuration Byte UCONFIG0 ....................................................................................4-6
4-4 Configuration Byte UCONFIG1 ....................................................................................4-7
4-5 Internal/External Address Mapping (RD1:0 = 00 and 01)...........................................4-10
4-6 Internal/External Address Mapping (RD1:0 = 10 and 11)...........................................4-11
4-7 Binary Mode Opcode Map..........................................................................................4-15
4-8 Source Mode Opcode Map ........................................................................................4-15
5-1 Word and Double-word Storage in Big Endien Form ...................................................5-3
5-2 Program Status Word Register...................................................................................5-18
5-3 Program Status Word 1 Register................................................................................5-19
6-1 Interrupt Control System ..............................................................................................6-2
6-2 Interrupt Enable Register .............................................................................................6-6
6-3 Interrupt Priority High Register .....................................................................................6-8
6-4 Interrupt Priority Low Register......................................................................................6-8
6-5 The Interrupt Process...................................................................................................6-9
6-6 Response Time Example #1 ......................................................................................6-11
6-7 Response Time Example #2 ......................................................................................6-12
7-1 Port 1 and Port 3 Structure...........................................................................................7-3
7-2 Port 0 Structure ............................................................................................................7-3
7-3 Port 2 Structure ............................................................................................................7-4
7-4 Internal Pullup Configurations ......................................................................................7-7
8-1 Basic Logic of the Timer/Counters ...............................................................................8-2
8-2 Timer 0/1 in Mode 0 and Mode 1 .................................................................................8-4
8-3 Timer 0/1 in Mode 2, Auto-Reload................................................................................8-5
8-4 Timer 0 in Mode 3, Two 8-bit Timers............................................................................8-6
8-5 TMOD: Timer/Counter Mode Control Register.............................................................8-7
8-6 TCON: Timer/Counter Control Register .......................................................................8-8
8-7 Timer 2: Capture Mode ..............................................................................................8-11
8-8 Timer 2: Auto Reload Mode (DCEN = 0)....................................................................8-12
8-9 Timer 2: Auto Reload Mode (DCEN = 1)....................................................................8-13
8-10 Timer 2: Clock Out Mode............................................................................................8-15
8-11 T2MOD: Timer 2 Mode Control Register....................................................................8-16