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Intel 8XC251SA - Page 427

Intel 8XC251SA
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C-25
REGISTERS
SCON
Address: 98H
Reset State: 0000 0000B
Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode
select bits and the interrupt flag bits.
7 0
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number
Bit
Mnemonic
Function
1 TI Transmit Interrupt Flag Bit:
Set by the transmitter after the last data bit is transmitted. Cleared by
software.
0 RI Receive Interrupt Flag Bit:
Set by the receiver after the last data bit of a frame has been received.
Cleared by software.
SP
Address: S:81H
Reset State: 0000 0111B
Stack Pointer. SP provides SFR access to location 63 in the register file (also named SP). SP is the
lowest byte of the extended stack pointer (SPX = DR60). The extended stack pointer points to the
current top of stack. When a byte is saved (PUSHed) on the stack, SPX is incremented, and then the
byte is written to the top of stack. When a byte is retrieved (POPped) from the stack, it is copied from
the top of stack, and then SPX is decremented.
7 0
SP Contents
Bit
Number
Bit
Mnemonic
Function
7:0 SP.7:0 Stack Pointer:
Bits 0–7 of the extended stack pointer, SPX (DR60).

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