Intel E810-CQDA2T - Reading Status of the DPLL

Intel
®
Ethernet Network Adapter E810-CQDA2T
User Guide
26 722960-002
3. SMA2 as 1PPS output:
# echo 2 2 > /sys/class/net/$ETH/device/ptp/ptp*/pins/SMA2
Note: Configurations (1 and 3) or (2 and 3) can be enabled at the same time, but not (1, 2, and 3).
4.9 Reading Status of the DPLL
The E810-CQDA2T driver exposes a simple debugfs interface that enables monitoring of the on-board
DPLL device state.
Note: The main purpose of this interface is for debug only. The debugfs interface is not available
when using Secure Boot option. All of the information is available using the pin_cfg or
dpll_<X>_ref_pin/dpll_<X>_state option as detailed in Section 4.11, “Advanced DPLL
Configuration”.
Note: Because of a known limitation, the Phase offset field might show incorrect values. This will
be fixed in the future releases.
# export ETH=enp1s0f0
# export PCI_SLOT=`grep PCI_SLOT_NAME /sys/class/net/$ETH/device/uevent | cut -c 15-`
#
# cat /sys/kernel/debug/ice/0000:82:00.0/cgu
Found ZL80032 CGU
DPLL Config ver: 1.3.0.1
DPLL FW ver: 6201
CGU Input status:
| | priority | |
input (idx) | state | EEC (0) | PPS (1) | eSync fail |
----------------------------------------------------------------
CVL-SDP22 (0) | invalid | 255 | 5 | N/A |
CVL-SDP20 (1) | invalid | 255 | 4 | N/A |
C827_0-RCLKA (2) | invalid | 8 | 8 | N/A |
C827_0-RCLKB (3) | invalid | 9 | 9 | N/A |
SMA1 (4) | invalid | 3 | 3 | N/A |
SMA2/U.FL2 (5) | invalid | 2 | 2 | N/A |
GNSS-1PPS (6) | valid | 0 | 0 | N/A |
EEC DPLL:
Current reference: GNSS-1PPS
Status: locked_ho_acq
PPS DPLL:
Current reference: GNSS-1PPS
Status: locked_ho_acq
Phase offset [ns]: -717
The first section of the log shows the status of CGU inputs (references), including its index number.
Active references currently selected are listed in Section 4.2. EEC Ethernet equipment clock (DPLL0)
skips the 1PPS signal received on the CVL-SDP20 pin.
The second section lists all internal DPLL units. ECC (DPLL0) driving the internal clocks and PPS (DPLL1)
driving all 1PPS signals.
The E810-CQDA2T supports embedded sync (eSync), including embedded pulse per second (ePPS),
The third section talks about the eSync, if it is enabled, as detailed in Section 4.11, “Advanced DPLL
Configuration”.