Intel
®
Ethernet Network Adapter E810-CQDA2T
User Guide
30 722960-002
Set freq to 10 MHz on input pin 4: DPLL will lock only if 10 MHz signals arrive on SMA1 and it has
been enabled for input.
# echo "in pin 4 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg
Set freq to 10 MHz on output pin 1: SMA2 will drive 10 MHz signal with embedded 1PPS if it has
been enabled for output.
# echo "out pin 1 freq 10000000 eSync 1" > /sys/class/net/$ETH/device/pin_cfg
Disable input pin 2: DPLL will ignore anything on pin 2.
# echo "in pin 2 enable 0" > /sys/class/net/<dev>/device/pin_cfg
Set Ref-Sync_pair on pin 0 & 1 (SDPs)
# echo "in pin 1 e_ref_sync 2" > /sys/class/net/$ETH/device/pin_cfg
Set freq to 1 Hz (1PPS) on input pin 4: DPLL will lock only if 10 MHz signals arrive on SMA1 and it
has been enabled for input with phase delay of 4 ns.
# echo "in pin 4 freq 1 phase_delay 4000" > /sys/class/net/$ETH/device/pin_cfg
4.11.2 dpll_<X>_ref_pin/dpll_<X>_state Machine Readable Interface
# export ETH=enp1s0f0
To find out which pin the DPLL0 (EEC DPLL) is locked on, check the dpll_0_ref_pin:
# cat /sys/class/net/$ETH/device/dpll_0_ref_pin
To check the state of the DPLL0 (EEC DPLL), check the dpll_0_state:
# cat /sys/class/net/$ETH/device/dpll_0_state
DPLL_UNKNOWN = -1,
DPLL_INVALID = 0,
DPLL_FREERUN = 1,
DPLL_LOCKED = 2,
DPLL_LOCKED_HO_ACQ = 3,
DPLL_HOLDOVER = 4
To find out which pin the DPLL1 (PPS DPLL) is locked on, check the dpll_1_ref_pin:
# cat /sys/class/net/$ETH/device/dpll_1_ref_pin
To check the state of the DPLL1 (PPS DPLL), check the dpll_1_state:
# cat /sys/class/net/$ETH/device/dpll_1_state
The dpll_0_state interface used by synce4l as well.
Note: The user application can monitor the dpll_<X>_state and dpll_<X>_ref_pin to detect the
DPLL status changes. These changes will be visible in the dmesg as well.
Note: The application can also check the DPLL name in the dpll_<X>_name file.
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