Intel E810-CQDA2T - Page 29

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Intel
®
Ethernet Network Adapter E810-CQDA2T
User Guide
out
| pin| enabled| dpll| freq| esync|
| 0| 1| 1| 1| 0|
| 1| 1| 1| 1| 0|
| 2| 1| 0| 156250000| 0|
| 3| 1| 0| 156250000| 0|
| 4| 1| 0| 156250000| 0|
| 5| 1| 1| 1| 0|
| 6| 1| 1| 1| 0|
In the “in” table. the pin numbers are referred from the DPLL Priority See Section 4.2, “DPLL Priority”.
In the “out” table pin 0 is SMA1 pin 1 is SMA2, all the other values do not modify.
Changing the DPLL priority list:
# echo "prio <prio value> dpll <dpll index> pin <pin index>" > \ /sys/class/net/$ETH/
device/pin_cfg
where:
Note: A prio value 15 disables the input for synchronization.
Example:
Set priority 1 for pin 3 on DPLL 0:
# export ETH=enp1s0f0
# echo "prio 1 dpll 0 pin 3" > /sys/class/net/$ETH/device/pin_cfg
Changing input/output pin configuration:
# echo "<direction> pin <pin index> <config>" > /sys/class/net/$ETH/device/pin_cfg
where:
Note: The eSync setting has meaning only with the 10 MHz frequency, you need to have eSync
to have the same setting in both ends of the SMA. eSync can be enabled only for the MA's
(input pin 4 / 5 and output pin 0 /1)
Example:
# export ETH=enp1s0f0
prio value = Desired priority of configured pin [0-9]
dpll index = Index of DPLL being configured [0:EEC (DPLL0), 1:PPS (DPLL1)]
pin index = Index of pin being configured [0-8]
direction = pin direction being configured [“in”: input pin, “out”: output pin]
pin index = index of pin being configured [for in 0-8 (see DPLL priority section); for out 0:
SMA1 1: SMA2]
config = list of configuration parameters and values:
[ "freq <freq_value_in_Hz>",
"phase_delay <phase_delay_value_in_ns>" // NOT used for out,
"eSync <0:disabled, 1:enabled>"
"e_ref_sync <0:disabled, 1:eSync enabled 2:Ref_Sync enabled>"
"enable <0:disabled, 1:enabled>" ]