Intel E810-CQDA2T - 1 PPS Signals from E810 Device to DPLL; 1 PPS Signals from the DPLL to E810 Device; GNSS Module Interface

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Intel
®
Ethernet Network Adapter E810-CQDA2T
User Guide
4.12 1PPS Signals from E810 Device to DPLL
The E810-CQDA2T implements two 1PPS signals coming out of the MAC (E810 device) to the DPLL.
They serve as the frequency reference (CVL-SDP20) and as both phase and frequency reference (CVL-
SDP22) signals.
To enable a periodic output, write five integers into the file: channel index, start time seconds, start
time nanoseconds, period seconds, and period nanoseconds. To disable a periodic output, set all the
seconds and nanoseconds values to zero.
Note: From firmware version 4.20 and onward, Intel recommends to use a 10 MHz signal on SDP20.
1. To enable the frequency reference pin 10 MHz (CVL-SDP20):
# echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period
2. To enable the phase and frequency reference pin (CVL-SDP22):
# echo 2 0 0 1 0 > /sys/class/net/$ETH/device/ptp/ptp*/period
3. To disable the phase reference pin (CVL-SDP20):
# echo 1 0 0 0 0 > /sys/class/net/$ETH/device/ptp/ptp*/period
4. To disable the phase and frequency reference pin (CVL-SDP22):
# echo 2 0 0 0 0 > /sys/class/net/$ETH/device/ptp/ptp*/period
Note: Because of a known driver limitation, before enabling the periodic outputs to the DPLL, make
sure that your PHC is synchronized (wait for stable ptp4l connection with dual digit offset). If
you need to do a jump on the PHC clock (like restarting ptp4l), you must to disable 1PPS and
10 MHz signal to DPLL. If the clock jumped, the periodic outputs to the DPLL might not ever
show a “valid” state in the CGU Linux interface. To restore correct operation of DPLL, reload
the driver:
# rmmod ice; modprobe ice
Note: Enabling the phase and frequency reference signal (CVL-SDP22) on the adapter without
external reference (ptp4l) is not recommended and might cause a frequency drift.
4.13 1PPS Signals from the DPLL to E810 Device
The DPLL automatically delivers two 1PPS signals to the E810 device on pin 21 and 23. These signals
can be used to synchronize the E810 to the DPLL phase with the ts2phc program. The E810 will capture
the timestamp when the 1PPS signal arrives.
4.14 GNSS Module Interface
Intel recommends disabling UART1 and UART2 interfaces on the GNSS receiver. To do that, use:
1. Disable UART1 in RAM, and Flash:
# ubxtool -v 1 -w 1 -P 29.20 -z CFG-UART1-ENABLED,0,5
Or open two terminals and run:
# cat /dev/gnssX //Terminal 1
# echo -ne "\xb5\x62\x06\x8a\x09\x00\x00\x05\x00\x00\x05\x00\x52\x10\x00\x05\x80"
> /dev/gnssX //Terminal 2