Remote Control
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Register. These bits do not latch, and their states (0 or 1) are solely dependent
on the summary messages (0 or 1). For example, if the Standard Event Status
Register is read, its register will clear. As a result, its summary message will
reset to 0, which in turn will clear the ESB bit in the Status Byte Register.
Bit B6 in the Status Byte Register is either:
The Master Summary Status (MSS) bit, sent in response to the *STB?
Command, indicates the status of any set bits with corresponding enable bits
set.
The Request for Service (RQS) bit, sent in response to a serial poll, indicates
which device was requesting service by pulling on the SRQ line.
For a description of the other bits in the Status Byte Register, see “Common
commands, *STB?”
The IEEE-488.2 standard uses the following common query command to read
the Status Byte
Register: *STB?.
When reading the Status Byte Register using the *STB? command, bit B6 is
called the MSS bit. None of the bits in the Status Byte Register are cleared
when using the *STB? command to read it.
The IEEE-488.1 standard has a serial poll sequence that also reads the Status
Byte Register and is better suited to detect a service request (SRQ). When
using the serial poll, bit B6 is called the RQS bit. Serial polling causes bit B6
(RQS) to reset. Serial polling is discussed in more detail later in this section
entitled “Serial Poll and SRQ.”
Any of the following operations clear all bits of the Status Byte Register:
Cycling power.
Sending the *CLS common command
Note: The MAV bit may or may not be cleared.
1.7.2 Service request enable register
This register is programmed by you and serves as a mask for the Status
Summary Message bits (B0, B2, B3, B4, B5, and B7) of the Status Byte
Register. When masked, a set summary bit in the Status Byte Register cannot
set bit B6 (MSS/RQS) of the Status Byte Register. Conversely, when unmasked,
a set summary bit in the Status Byte Register sets bit B6.
A Status Summary Message bit in the Status Byte Register is masked when the
corresponding bit in the Service Request Enable Register is cleared (0). When
the masked summary bit in the Status Byte Register sets, it is ANDed with the
corresponding cleared bit in the Service Request Enable Register. The logic “1”
output of the AND gate is applied to the input of the OR gate and, thus, sets the
MSS/RQS bit in he Status Byte Register.
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