Test 101.1 — TESTCAL
Bank A/D
Expected Value <none specified>
Limits <none specified>
Inputs Open
Description
TESTCAL is a way to calibrate the unit with internal references so that
the remaining tests can be displayed in the form of voltages. Given that there
are errors in the internal references and in the A/D circuitry, the voltages on
the display of the unit may vary from the value that is measured at A/D-IN
with a calibrated test meter. The values on the display of the unit under test
are values that are relative to the internal references.
This test has the same set up as the 100.1 and 100.2 tests. The A/D makes
a conversion of the signal zero and stores the value in the form of A/D counts
to be used in the next phase of the test. There is no fault message for this test.
Measure 0V at A/D-IN.
Bit patterns
Bit pattern Register
QQ
87654321
—U106—
110v1111
QQ
87654321
—U109—
00101111
QQ
87654321
—U134—
1v10000v
—U130—
11111101
QQ
87654321
—U121—
01110010
ACDC_STB
MUX_STB
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
Troubleshooting 2-25