Troubleshooting
2-18
Line voltage (110V/220V) selection circuit
This circuit automatically selects the proper power line
voltage setting for the instrument. The line selection
circuit derives its power from the AC1 and AC2 lines
on the primary side of the transformer. RectiÞer CR101
applies approximately +18V to regulator U103. The
output of U103 provides the +8V for the line voltage se-
lection circuit and the HI/LO voltage control circuit.
U106 is a comparator that has a +4V reference (via volt-
age divider R125 and R126) applied to its non-invert-
ing input. The inverting input monitors the voltage on
C111. When the voltage at the inverting input is greater
than 4V, the output of U106 goes low and turns on FET
Q103. With Q103 on, +8V will be applied to the
+RELAY1 line which energizes relay K101 to select the
110V setting. Conversely, when the voltage at the in-
verting input is less than 4V, the output of U106 goes
high and turns off Q103. With Q103 off, the +8V is re-
moved from K101 and thus, the line voltage setting de-
faults to 220V.
The AC power line is tied to C111 through CR104, R227
and R114 via control line ACL. When the AC power
line voltage is less than approximately 135VAC, sufÞ-
cient charge remains on C111 to keep the inverting in-
put of U106 above 4V to ultimately energize K101
(110V setting). When the AC power line voltage is
greater than approximately 18VAC, charge will be
pulled from C111 dropping the voltage at the inverting
input of the comparator to less than 4V. This will de-en-
ergize K101 (220V setting).
HI/LO voltage control circuit
This circuit automatically selects the appropriate HI/
LO setting for the available power line voltage. During
power-up, the line voltage is rectiÞed (CR100), divided
(R103 and R105, or R102 and R105) and applied to the
base of Q101.
If the voltage level at the base of Q101 is high (above
zener VR101), the transistor will turn on and apply
power to the ISO1+ and ISO1- lines. With power ap-
plied to ISO1+ and ISO1-, U105 will turn on and allow
Q105 to be forward biased. With U105 and Q105 on,
TRIG of U110 will be pulled low and allow its output
(OUT) to latch at +8V which will turn on FET Q102.
With Q102 on, the -RELAY2 line will be connected to
common, and thus energize K100 (HI setting).
If the power line voltage decreases to a low level, U105
will turn off, but the output of U110 will remain latched
at +8V. However, the LOW line will be driven low turn-
ing on U109. With U109 and Q106 on, +8V will be ap-
plied to THR of U110 forcing its output (OUT) to reset
to low. With the gate of Q102 low, the FET will turn off
and open the relay coil circuit for K100 (LO setting).
The LOW line is controlled by comparator U628. The
inverting input of the comparator is connected to the
2.5V reference. The non-inverting input monitors (via
divider R709 and R711) C611. As previously explained,
the typical power line voltage level will apply around
7.5V to C611. However, if the line voltage decreases
such that the voltage on C611 becomes less than 6V, the
voltage level on the non-inverting input of the compar-
ator will drop below 2.5V causing its output (LOW
line) to go low.
2.10.3 Built-in test documentation
The information in this paragraph provides documen-
tation for each Built-In Test. Paragraph 2.5 explains
how to use the Built-In Test.
The following documentation is provided for each
Built-In Test:
1. Test Type Ñ Some tests are pass/fail type tests
while others are circuit exercises that are used for
subsequent tests.
2. Failure Analysis Ñ For pass/fail type tests, a sum-
mary is provided to explain the cause of the failure.
3. Description Ñ Provides a description of the circuit
being tested.
4. Schematic Reference Ñ Directs you to the appro-
priate schematic(s) for the circuit being tested.
5. High Suspect Components Ñ When appropriate,
possible defective components and/or circuits are
listed. It is left to the expertise of the repair techni-
cian to pin-point the problem.
6. Shift Registers Ñ For tests starting with 200.1, the
logic states for the control shift registers are pro-
vided. After one of these tests is manually run, you
can check the registers for the correct logic levels.
Tables 2-10 through 2-12 provide functional de-
scriptions for the register bits.
7. Multiplexer Ñ For manually run tests that exercise
the multiplexer (U511), you can use Table 2-13 to
check the logic levels on its control lines.
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