Lake Shore Model 331 Temperature Controller User’s Manual
6.1.3 Status Registers
There are two status registers: the Status Byte Register described in Paragraph 6.1.3.1, and the
Standard Event Status Register in Paragraph 6.1.3.2.
6.1.3.1 Status Byte Register and Service Request Enable Register
The Status Byte Register contains six bits of information about the operation of the Model 331.
STATUS BYTE REGISTER FORMAT
Bit – 7 6 5 4 3 2 1 0
Weighting – 128 64 32 16 8 4 2 1
Bit Name –
Ramp
Done
SRQ ESB Error Alarm
Not
Used
Not
Used
New
A&B
If Service Request is enabled, any of these bits being set will cause the Model 331 to pull the SRQ
management line low to signal the BUS CONTROLLER. These bits are reset to zero upon a serial
poll of the Status Byte Register. These reports can be inhibited by turning their corresponding bits
in the Service Request Enable Register to off.
The Service Request Enable Register allows the user to inhibit or enable any of the status reports
in the Status Byte Register. The
QSRE command is used to set the bits. If a bit in the Service
Request Enable Register is set (1), then that function is enabled. Refer to the
QSRE command
discussion.
Ramp Done, Bit (7) – This bit is set when the ramp is completed.
Service Request (SRQ) Bit (6) – Determines whether the Model 331 is to report via the SRQ line.
If bits 0, 3, 4, 5 and/or 7 are set, then the corresponding bit in the Status Byte Register will be set.
The Model 331 will produce a service request only if bit 6 of the Service Request Enable Register
is set. If disabled, the Status Byte Register can still be read by the BUS CONTROLLER by means
of a serial poll (SPE) to examine the status reports, but the BUS CONTROLLER will not be
interrupted by the Service Request. The
QSTB common command will read the Status Byte
Register but will not clear the bits.
Standard Event Status (ESB), Bit (5) – When bit 5 is set, it indicates if one of the bits from the
Standard Event Status Register has been set. (Refer to Paragraph 6.1.3.2.)
Error, Bit (4) – This bit is set when there is an instrument error not related to the bus.
Alarm, Bit (3) – This bit is set when there is an alarm condition.
New A&B, Bit (0) – This bit is set when new data is available from the normal inputs.
6.1.3.2 Standard Event Status Register and Standard Event Status Enable Register
The Standard Event Status Register reports IEEE bus status of the Model 331.
STANDARD EVENT STATUS REGISTER FORMAT
Bit – 7 6 5 4 3 2 1 0
Weighting – 128 64 32 16 8 4 2 1
Bit Name – PON
Not Used
CME EXE DDE QYE
Not Used
OPC
Bits 2 and 6 are not used. The bus controller will only be interrupted with the reports of this register
if the bits have been enabled in the Standard Event Status Enable Register and if bit 5 of the
Service Request Enable Register has been set.
The Standard Event Status Enable Register allows the user to enable any of the Standard Event
Status Register reports. The Standard Event Status Enable command (
QESE) sets the Standard
Event Status Enable Register bits. If a bit of this register is set, then that function is enabled. To set
a bit, send the command
QESE with the bit weighting for each bit you want to be set added
together. See the
QESE command discussion for further details.
6-4 Remote Operation
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