Lattice Semiconductor CrossLink-NX User Manual

CrossLink-NX Evaluation Board
User Guide
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FPGA-EB-02028-1.3 19
6. Control Buses – I
2
C, UART, and SPI
This section describes the topology of the various configuration and communication buses.
6.1. I
2
C
The CrossLink-NX Evaluation Board uses the I
2
C bus to support CrossLink-NX configuration, and optionally to support
Raspberry Pi communication. The global I
2
C bus has the signal names SDA and SCL and they are routed close to
Raspberry Pi header as shown in Figure 4.1 and in more detail in Figure 6.1.
Raspberry Pi connector is connected to a dedicated CrossLink-NX GPIO bank with a direct local I
2
C bus. Local I
2
C bus can
optionally connect to the global I
2
C bus through resistors. The local I
2
C connections are summarized in Table .
FTDI 2232H (UI)
BDBUS0
BDBUS1/2
SDA
SCL
Instantiated I
2
C
Resistors (R18, R19)
RASP_ID_SD
RASP_ID_SC
Bank6 (U3)
Bank1 (U3)
SDA
SCL
TXD_UART
RXD_UART
Figure 6.1. I
2
C Architecture and UART Options
Table 6.1. I
2
C Global Bus Connections
CrossLink-NX Bank
Component
(Reference)
Header Pin
CrossLink-NX -
85 Ball
Local Signal Name (Global I
2
C Signal)
Resistor
6
Raspberry Pi
header (JP5)
27
M7
RASP_ID_SD (SDA)
R40 (DNI)
28
M4
RASP_ID_SC (SCL)
R39 (DNI)
6.2. UART Topology
The board provides support for UART configuration by providing an uninstalled connection between the FTDI and
CrossLink-NX. Two 0 Ω resistors (R16 and R17) can be installed to connect Port 1 to two general purpose I/O (PR8A/F16
and PR10A/F18) in Bank 6 as shown in Figure 6.1.
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Lattice Semiconductor CrossLink-NX Specifications

General

Brand	Lattice Semiconductor
Model	CrossLink-NX
Category	Motherboard
Language	English