Lattice Semiconductor CrossLink-NX - Figure 1.2. Bottom View of Crosslink-NX Evaluation Board

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CrossLink-NX Evaluation Board

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8 FPGA-EB-02028-1.3

200 MHZ OSC for Serdes (U5) 125 MHZ OSC for Serdes (U4)

Figure 1.2. Bottom View of CrossLink-NX Evaluation Board

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Main Page

Default Chapter3
- Table of Contents3
- Acronyms in this Document5
1 Introduction6
2 Jumpers and Test Connection12
- Figure 2.1. Top View of Crosslink-NX Evaluation Board - Jumper Locations12
- Table 2.1. Jumper Table13
3 Power Scheme14
- Figure 3.1. Board Power Scheme14
- Table 3.1. Crosslink-NX VCCIO Supply Options14
4 Programming and I 2 C15
5 Crosslink-NX Clock Sources18
- Table 5.1. Clock Sources18
6 Control Buses - I C, UART, and SPI19
7 Leds and Switches21
8 Headers/Connectors and LIFCL-40 Device Ball Mapping23
9 Software Requirements30
10 Storage and Handling30
11 Ordering Information30
- Table 11.1. Ordering Information30
Appendix A. Crosslink-NX Evaluation Board Schematics31
Appendix B. Crosslink-NX Evaluation Board Bill of Materials45
Appendix C. Fast Configuration Issues53
Appendix D. Schematics Updates for ADC Test54

Lattice Semiconductor CrossLink-NX - Figure 1.2. Bottom View of Crosslink-NX Evaluation Board

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