Lattice Semiconductor CrossLink-NX - Parallel Configuration Header; ADC Test Header

CrossLink-NX Evaluation Board
User Guide
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FPGA-EB-02028-1.3 29
8.8. Parallel Configuration Header
The J27 header is used to access the SPI port of the CrossLink-NX.
Table 8.8. J27 Header Pin Connections
J27Pin Name
Signal Name
LIFCL-40 Ball
1
VCCIO2
—
2
VCCIO2
—
3
FMC_TCK
P19
4
PS_POR_B
N19
5
GND
—
6
GND
—
7
FMC_TDI
P20
8
FMC_PRSNT
N20
9
FMC_TDO
P17
10
FMC_SCL
M20
11
GND
—
12
GND
—
13
FMC_TMS
P18
14
FMC_SDA
M19
8.9. ADC Test Header
Table 8.9. J26 Header Pin Connections
J26 Pin Name
Signal Name
LIFCL-40 Ball
1
GND
—
2
GND
—
3
J24 PIN3
—
4
GND
—
5
J25 PIN3
—
6
GND
—
7
GND
—
8
GND
—
9
ADC_IN1P
T17
10
GND
—
11
ADC_IN1N
U17
12
GND
—
13
GND
—
14
GND
—
15
VREF2_CON
—
16
GND
—
17
GND
—
18
GND
—
19
VREF1_CON
—
20
GND
—
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