LG DR1F9H User Manual

4-39
MAJOR IC INTERNAL BLOCK DIAGRAM
LIC121 (AN22113A) : FEP(RF) ANALOG SIGNAL PROCESSOR
• BLOCK DIAGRAM
Input Block
TEC Block
LPOS Block
WBL/LPP Block
OFTR Block
OPC&ASENV
Block
RFEQ Block
JLINE Block
LOGIC Block
APC Block
MPX Block
FIN
STMD
STMDN
STMOUT
SE01 SE02
TC
WBLDIF
ASENV/ LPPM
LPPS WBL OFTR VPD FPDN SDAT SCK SEN RSDAT RSEN
EIN
TR3 TR4
AIN/TR1
B
IN/TR2
HIN/Fo1
GIN/Fo2
VREF
CD/DVD
Switch
S/H
&
VGA
MPX
MPX
MPX
MPX
MPX
MPX
MPX
DPD Block
TCTI Block
BDO Block
FOCUS
PPTE
Block
VREF
Block
RF Gene Block
GATE
Block
Operation Circuit
SMFEP
SDAAOUT SDABOUT
SPLAOUT
SDACOUT SDADOUT
SPLBOUT
SRFMA
SRFMD
SRFMB
SRFMC
SMTEP
SMTEN
CHP0FT
COFTR
SLP14
SLP23
SMFEPN
SSFEP
SSFEPN
SMTEP
SMTEN
SSTEP
SSTEN
SDAAOUT SDABOUT
SDACOUT SDADOUT
SDPDTEP
SRFMA
SRFMD
SRFMB
SRFMC
SDPDTEN
SPLAOUT SPLBOUT
SPOF
TCOP
TCO
TCON
TIOP
TIO
SBDOAS
TION
VGA
VGA
COMP.
PK
ENV
PK
ENV
COMP.
VGA/
Bypass
VGA/
Bypass
M
P X
M
P
X
DPD TE
Dtetction
TC/TI
Dtetction
HDVREF
VHALF
VREF08
RFP
CDRFP
RFN
CDRFN
BDO
RF OUT
RFIN1 RFIN2
EQOUTP
EQOUTN
VREF
GATE
All
Sum
VG
A
Group delay
compensation
SW
To
Each Block
PK
ENV
VGA
COMP.
Lve1
Shift
LPF
MPX
TECENV
SLPOS2
SLP23
SLP14
LPF
SLPOS1
SSTEP
SSTEN
VGA S/H VGA
VGA
WBL
Detection
LPP
Detection
BAL BAL
AGC/
Bypass
AGC/
Bypass
S/H VGA
Amp
COMP.
VGA
VGA
VGA VGA
S/H VGA
LPF
Bypass
+
-
+
+
-
-
+
+
+
+
_
_
+ +
_ _
+
LPF
PK
ENV
BT
ENV
ATT
Amp EQ
0FST
To Each Block
To Each Block
To MPX
JLINE
LOGIC
COMP.
CLMP.
-
VGA VGA VGA S/H
S/H S/H
LPF/
Bypass
ATT
SEL

LG DR1F9H Specifications

General

Brand	LG
Model	DR1F9H
Category	DVD Recorder
Language	English