R8C/2A Group, R8C/2B Group 1. Overview
Rev.1.00 Feb 09, 2007 Page 8 of 55
REJ03B0182-0100
1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
Figure 1.3 Block Diagram
D/A converter
(8 bits
u 2)
R8C/Tiny Series CPU core
Memory
ROM
(1)
RAM
(2)
Multiplier
R0H R0L
R1H
R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
8
Port P1
8
Port P3
3 2
Port P4
8
Port P0
8
Port P2
5
Port P5
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Timers
Timer RA (8 bits u 1)
Timer RB (8 bits u 1)
Timer RC (16 bits u 1)
Timer RD (16 bits u 2)
Timer RE (8 bits u 1)
Timer RF (16 bits u 1)
UART or
clock synchronous serial I/O
(8 bits u 3)
I
2
C bus or SSU
(8 bits u 1)
Peripheral functions
Watchdog timer
(15 bits)
A/D converter
(10 bits
u 12 channels)
LIN module
8
Port P6
7
Port P8
R8C/2A Group, R8C/2B Group 1. Overview
Rev.1.00 Feb 09, 2007 Page 9 of 55
REJ03B0182-0100
1.4 Pin Assignment
Figure 1.4 shows Pin Assignment (Top View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin
Number.
Figure 1.4 Pin Assignment (Top View)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
R8C/2A Group
R8C/2B Group
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1 3 4 5 6 7 8 9 10 11 12 13 14 15 162
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P1_0/Kl0/AN8
P3_5/SCL/SSCK
P3_7/SSO
VCC/AVCC
VREF
P0_7/AN0/DA1
VSS/AVSS
P0_6/AN1/DA0
P0_5/AN2/CLK1
P6_1
P6_2
P0_3/AN4
P0_2/AN5
P0_0/AN7
P0_1/AN6
P0_4/AN3
P8_2/TRFO02
P2_6/TRDIOC1
P2_5/TRDIOB1
P2_4/TRDIOA1
P2_3/TRDIOD0
P2_2/TRDIOC0
P2_1/TRDIOB0
P2_0/TRDIOA0/TRDCLK
P1_7/TRAIO/INT1
P1_6/CLK0
P1_5/RXD0/(TRAIO)/(INT1)
(2)
P8_6
P8_5/TRFO12
P8_3/TRFO10/TRFI
P8_4/TRFO11
P1_4/TXD0
P1_1/Kl1/AN9
P8_1/TRFO01
P8_0/TRFO00
P6_0/TREO
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P6_5/(CLK1)/CLK2
(2)
P6_4/RXD2
P6_3/TXD2
P3_1/TRBO
P3_6/(INT1)
(2)
P3_2/(INT2)
(2)
P1_2/Kl2/AN10
P1_3/Kl3/AN11
P3_0/TRAO
P3_3/SSI
P2_7/TRDIOD1
P5_0/TRCCLK
P5_1/TRCIOA/TRCTRG
P5_2/TRCIOB
P5_3/TRCIOC
P5_4/TRCIOD
VCC/AVCC
P4_6/XIN
VSS/AVSS
P4_7/XOUT
(1)
P4_4/XCOUT
P4_3/XCIN
P3_4/SDA/SCS
MODE
RESET
NOTES:
1. P4_7/XOUT are an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
PLQP0064KB-A(64P6Q-A)
PLQP0064GA-A(64P6U-A)
(top view)
Pin
No
Port Name I/O Use Name
PortSetup
Note
Act. Init
57 P05/AN2/CLK1 I/O O NO USE - L Open
58 P06/AN1/DA0 I/O O NO USE - L Open
59 VSS/AVSS I I GND - - GND
60 P07/AN0/DA1 I/O O I2C_RST L H Reset Output
61 VREF - - +3.3V - - Reference Input
62 VCC/AVCC - - +3.3V - - +3.3V
63 P37/SSO I/O I NMI L L Standby Input
64 P35/SCL/SSCK I/O SCL SCL - H SCL Reserved
IC01 : R5F2122AASNFP [SR6003 : USB]
IC01 / IC61: R5F2122AASNFP
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