Marantz SR6003 - Page 96

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2 Device Overview
256K
Bytes
RAM
Bytes
ROM
768K
Memory Controller
C67x+
DSP Core
Program
Cache
Crossbar Switch
EMIF
dMAX
McASP0
SPI1
McASP1
I2C0
I2C1
RTI
SPIO
McASP2
PLL OSC
ASYNC
FLASH
100-MHz/
133-MHz
SDRAM
DSP
Host
Microprocessor
Audio Zone 1
SPI or I2C
Control (optional)
Audio Zone 2
Audio Zone 3
CODEC, DIR,
ADC, DAC, DSD,
Network
Network
ADC, DAC, DSD,
CODEC, DIR,
Digital Out
DSP Control
SPI or I2C
5 Independent Audio
Zones (3 TX + 2 RX)
16 Serial Data Pins
2.1 Enhanced C67x+ CPU
2.2 Efficient Memory System
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B
Floating-Point Digital Signal Processors
SPRS297E–JULY 2005–REVISED JULY 2007
The TMS320DA708/B/TMS320DA788B devices are the second generation of Texas Instruments'
Aureus™ family of high-performance 32-/64-bit floating-point digital signal processors.
Note: The TMS320DA788B supports DTS® 5.1, DTS-ES™ 6.1, DTS Neo:6™, DTS 96/24™, and DTS-ES
96/24™. If the application requires DTS algorithms, the TMS320DA788B DSP should be used.
Figure 2-1 illustrates a high-level block diagram of the device and other devices to which it may typically
connect. An overview of each major block follows the figure.
Figure 2-1. DA708/B/DA788B Aureus™ Audio DSP System Diagram
The C67x+ CPU is an enhanced version of the C67x CPU used on the DA6xxx first-generation Aureus™
DSP. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and
floating-point performance per clock cycle. At 266 MHz, the CPU is capable of a maximum performance of
2128 MIPS/1596 MFLOPS by executing up to eight instructions (six of which are floating-point
instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision
floating-point, and 64-bit double-precision floating-point arithmetic.
The memory controller maps the large on-chip 256K-byte RAM and 768K-byte ROM as unified
program/data memory. Development is simplified since there is no fixed division between program and
data memory size as on some other devices.
The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.
Up to four simultaneous accesses are supported:
Device Overview4 Submit Documentation Feedback
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2.15 Device Block Diagram
Program/Data
RAM
256K Bytes
256
256
Program/Data
ROM Page1
256K Bytes
256
256
256K Bytes
ROM Page3
Program/Data
Program/Data
ROM Page2
256K Bytes
3232
DMPPMP
CSP 32
256
Program
Cache
32K Bytes
64
D1
Data
R/W
R/W
Data
D2
64
256
Program
FetchINTI/O
C67x+ CPU
Memory
Controller
32
High-Performance
Crossbar Switch
32
McASP DMA Bus
JTAG EMU
32
32
32
32
32
32
32
Peripheral Configuration Bus
EMIF
32
Events
In
32
MAX1MAX0
32
CONTROL
32
Interrupts
Out
I/O
dMAX
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
DIT Only
SPI1
SPI0
I2C1
I2C0
RTI32
PLL
Peripheral Interrupt and DMA Events
32
32
32
32
Aureus TMS320DA708, TMS320DA708B, TMS320DA788B
Floating-Point Digital Signal Processors
SPRS297E–JULY 2005–REVISED JULY 2007
Figure 2-3. DA708/B/DA788B DSP Block Diagram
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IC21 : TMS320DA788B