2070LX Controller – User Manual 19
Version 1.0
Octal buffers/drivers
These LV541A devices are used for driving the communication, status and control lines between the
processor on engine board and the related circuitry on Host Board; these lines are SP-1 to SP-8, SPI bus,
CPULRESET, CPUACTIVE, POWERUP, DATAKEY present and USB signals.
These devices are used as voltage level translators because their inputs can be driven at either 5VDC or
3.3VDC allowing them to work in a mixed 3.3VDC/5VDC system environment.
The devices are permanently enabled; the 3-state control gates (OE1 or OE2) are tied to ground.
There are two types of buffer/drivers used:
LV541AP are used to “translate” the 5VDC level from Host Board signals to 3.3VDC level to be used on
Engine Board.
LV541AT are used to “translate” the 3VDC level from Engine Board signals to 5VDC level to be used on
Host Board.
Octal bus transceivers
These devices provide a data bus interface between the Processor and the memories (SRAM, FLASH).
They transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic
level at the direction-control input (DIR).
Processor writes data to memory by setting a high logic level at the DIR input; it reads data from memory
by setting a low logic level at the DIR input.
The output-enable (OE) is tied to ground so that the devices are permanently enabled.
USB transceiver
The USB transceiver interfaces the standard logic to the physical layer of the Universal Serial Bus. This
means that the Processor is in charge of the USB logic functionality and the transceiver is responsible of
the compliance, signal integrity and signal quality issues related to driving and receiving differential
signals.
Features:
The transceiver converts USB differential voltages to digital logic signal levels.
It converts the D+ and the D- line to single ended logic outputs.
It converts logic levels to different USB signals: it runs at low or high speed, it has selectable
output slope control, it meets the USB 1.1 drive template, it has low power standby mode.
The transceiver provides a differential I/O data bus (D+ and D-) for communications with the Host Board.
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