36
LED’s status indicators
The status indicator circuits for transmission and reception consist of an inverter gate, an LED and a
current limiting resistor in series.
The “SP3 Tx” and “SP5 Tx” LED status indicator circuits are driven by the corresponding single
ended transmission signal already isolated.
The “SP3 Rx” and “SP5 Rx” LED status indicator circuit are driven by the corresponding single
ended reception signal coming from the EIA-485 receiver at the isolated side.
The “SP3 ACTIVE” status indicator circuit consists in a current limiting resistor and an LED; it is
driven by the “S1” toggle switch. Indicator is turned on when switch is at “ON” position and turned
off when the switch is at the “OFF” position.
The “ACTIVE” LED status indicator circuit for the SP-5 consists of an LED and current limiting
resistor in series; this circuit is driven directly by the microcontroller.
o The Fast Flash (10Hz) condition means that the SP-5 communication is present.
o The Slow Flash (1Hz) condition means that the SP-5 communication is not present.
o If there is a steady condition either “ON” or “OFF” then there is a fault condition.
RESET
Processor has two input pins called /HALT and /RESET which are tied handled by the line /RESETH,
when this line is in LOW state then processor is said to be RESET. There are four sources for generating
the /RESETH line, the watchdog circuit, the supervisory circuit, the NRESET circuit and the BDM circuit.
Watchdog
A watchdog circuit is used to force a system reset and protect against system failures when the program
is not executed as expected. This circuit provides a means to escape from unexpected input conditions,
external events, or programming errors. The watchdog counter is cleared by the program periodically so
that it never reaches its timeout value, otherwise a system failure occurred and then a system reset is
applied to force the system back to a known starting point.
The circuit is implemented by using a D-Type flip—flop that receives two inputs from the processor
(watchdog control and the watchdog reset lines), its output (watchdog flag) goes to the watchdog input at
processor.
The watchdog control input presets the output to LOW state; watchdog reset serves as a clock input
transferring the input to the output, forcing the output to HIGH state because the input is tied to ground.
Watchdog flag keeps the watchdog status and it is monitored by the processor after the reset condition in
order to know if it was because a watchdog “no service” condition as a result of a program malfunction.
WDT enable shunt:
A watchdog timer enable shunt is provided on the module. It consists of a 3-positions header (JP1) and a
jumper to be placed at either ON or OFF position.
To Next Page
Loading...
Need help?
General
