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Each input bank is formed of two octal buffers, receives 16 inputs from the resistive network and sends
the corresponding 16-bits of information to the CPU through the data bus when its corresponding enable
input is asserted.
Bank 1 (formed by port 1 and port 2) handle the inputs 1 to 16.
Bank 2 (formed by port 3 and port 4) handle the inputs 17 to 32.
Bank 3 (formed by port 5 and port 6) handle the inputs 33 to 48.
Bank 4 (formed by port 7 and port 8) handle the inputs 49 to 64.
This lines for enabling and disabling the four input banks come from a 3-line to 8-line decoder. The
decoder accepts the lines A1, A2 and A3 from the address bus to select a bank, two active-low enable
inputs for the chip select and output enable and one active-high enable input for the line that clear the
output banks.
The parallel input ports’ stage is powered with ISO +5VDC.
Parallel outputs ports
64 outputs using ground-true logic are provided; outputs written as a logic “1” have sink-current capability
and outputs written as a logic “0” provide an open circuit. Each output is capable of driving 50 VDC and
sinking 150mA.
The 64 outputs are distributed on eight octal D-Type latches; in order to send these outputs to the field
connectors they are arranged into four 16-bit groups called output banks.
Each output bank is formed of two octal D-Type latches, receives 16-bits of information from the CPU
through the data bus and sends the corresponding 16 outputs to the field connectors at the positive edge
of the clock input.
Bank 1 (formed by port 1 and port 2) handle the outputs 1 to 16.
Bank 2 (formed by port 3 and port 4) handle the outputs 17 to 32.
Bank 3 (formed by port 5 and port 6) handle the outputs 33 to 48.
Bank 4 (formed by port 7 and port 8) handle the outputs 49 to 64.
This lines for enabling and disabling the four output banks come from a 3-line to 8-line decoder. The
decoder accepts the lines A1, A2 and A3 from the address bus to select a bank, two active-low enable
inputs for the chip select and output enable and one active-high enable input for the line that clear the
output banks.
The line for enabling/disabling the output banks is connected to the clock input pin of the corresponding
octal D-Type latch, when this input goes to high, information at the inputs are transferred to the outputs
on the positive going edge of the clock pulse. When the clock input is at either the high or low level, the
input signals have no effect at the outputs.
The parallel output ports’ stage is powered with ISO +5VDC.
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