CPU Card
5 - 1
CPU Card
The CPU Card contains the main injector operating program. Refer to
Figure 5.1 for a block diagram of the CPU Card. The CPU Card con
-
tains the following circuits:
CPU The Z-80 CPU U10 is supported by 512 Kbytes of EPROM, and 8
Kbytes of RAM. This processor provides a 16-bit address bus, an 8-bit
data bus, and several control lines for Read/Write, Interrupts, etc..
Clock Crystal Y2 (8 MHz) and clock generator chip U2, produce the 4 MHz
clock system for the CPU, and provide a Reset pulse when power is
first applied. This pulse resets the CPU, and ensures that the pro
-
gram starts at the beginning.
Memory CPU memory is comprised of one EPROM / PROM chip (U24), and
one RAM chip (U16). These chips connect the address and data
buses, and are controlled by both the enable lines from the memory /
I/O decoder, and the Read/Write lines from the CPU. EPROM chip
U24 is only accessed when switch SP2-2 is set to the “U24” position.
If this chip must be replaced, contact MEDRAD Service for a current
version EPROM.
Memory /
Input/Output
Decoder
The Memory / Input/Output Decoder, comprised of U23 and U26, pro-
vides:
• Control of the memory chips during read/write cycles
• Two major decode lines (MEMIO1 and MEMIO2: Pins 16
and 17) that are buffered and sent to the Input/Output Card
• Direction control for the data buffer
Bus Buffers The control lines from the CPU are buffered by U17, then sent to the
motherboard bus. The address bus is buffered by U18 and U19, then
sent to the motherboard bus. The flow of data is controlled by bidirec
-
tional buffer U20, which is controlled by the Memory / I/O Decoder.
Control and addressing lines flow away from the CPU, while the buff
-
ered data bus, can flow in either direction.
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