Input / Output Card
6 - 1
Input / Output Card
Through the I/O Card, the CPU:
• reads external switches and system event status
• operates external connections
• synchronizes and times the injection.
Refer to Figure 6.1 for a block diagram of the I/O Card.
Bus Buffers The control bus is buffered by U14, and the address bus is buffered by
U15. The bidirectional data bus is buffered and controlled by U22, with
direction control from I/O decoder U8.
Display Buffers Two address lines, and eight data lines, are buffered for the Display
Card by U16 and U19.
I/O Decoder Decoder U8, controlled by address and control lines, provides an
enable to programmable I/O (PIO) chips U5 and U6, counter/timer chip
(CTC) U4, and, provides data direction control for data buffer U22.
Parallel
Input/Output Chip
Parallel I/O chips permit the CPU to access external inputs, and to con-
trol outputs.
• PIO1 -- The inputs to U6 are the hand start switch, remote start
switch, and remote disarm input. Through the data buses, the CPU
can check the status of these inputs. Outputs from U6 include: The
film changer relay enables two injecting signals; the Armed signal,
and Head Indicator signals. Through the I/O chip, the CPU can turn
these outputs on and off.
Counter / Timer
Chip (CTC)
The CTC (U4) generates interrupt signals for the CPU. The interrupts
are prioritized and asynchronous with the system clock.
• Trigger 1: PPI memory error interrupt request. PPI primary and
backup memories are compared each time primary memory is read.
If primary and backup data values are not equal, an interrupt
request is generated.
6
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