Mitsubishi Electric MELSEC iQ-R-R04CPU - Module-By-Module Data Guarantee

16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
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16
Module-by-module data guarantee
In data communication, data is handled in units of 64 bits. Therefore, when data larger than 64 bits is handled, old and new
data may be mixed for each CPU module depending on the timing between data reading by the host CPU module and data
writing by other CPU modules/data receiving from other CPU modules. (Data inconsistency) To avoid this problem, the
system conducts the refresh operation by exchanging handshake signals between the CPU modules for guaranteeing refresh
data on a module-by-module basis.
1
2
3
10
11
50
51
100
101
102
1
1
1
1
1
1
1
1
1
101
101
1
1
1
2
3
10
11
50
51
100
101
102
10
50
100
1
2
3
10
11
50
51
100
101
102
100
50
100
0→1
D0,D1
0
0
0
0
0
D0,D1
0
0
0
0
0
0
0
0
0
0
D0,D1
0
0
0
0
0
D0,D1
0
0
0
0
0
SM 400
DINC D0
0→1
0→1 0→1 0→1
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Data change when the CPU module unit guarantee
is disabled
(Scan)
First scan
Second scan
Third scan
10th scan
11th scan
50th scan
51st scan
100th scan
101st scan
102nd scan
(Value) (Scan)
First scan
Fifth scan
10th scan
(Value)(Scan)
First scan
Second scan
Third scan
10th scan
11th scan
50th scan
51st scan
100th scan
101st scan
102nd scan
(Value)
Device memory CPU buffer memory Device memory Device memory Device memory
(Scan)
First scan
(Value)(Scan)
First scan
Second scan
(Value)
Time: (The time axis is
based on the CPU No.1.)
The CPU reflects (refreshes) the data in the END processing of each scan.
(Scan)
First scan
Second scan
Third scan
10th scan
11th scan
50th scan
51st scan
100th scan
101st scan
102nd scan
(Value) (Scan)
First scan
(Value)
CPU No.1 CPU No.2 CPU No.3
(Scan)
First scan
Second scan
Third scan
10th scan
11th scan
50th scan
51st scan
100th scan
101st scan
102nd scan
(Value)
Device memory CPU buffer memory
Data change when the CPU module unit guarantee
is enabled
Device memory
Device memory Device memory
(Scan)
First scan
(Value)(Scan)
First scan
(Value)
CPU No.4
Time: (The time axis is
based on the CPU No.1.)
CPU No.1
Device
CPU buffer memory
Device Device Device
Program
(2) The CPU No.1 reflects
(refreshes) the data in the
END processing of the
CPU No.1.
The CPU module unit guarantee
is enabled:
(3) The CPU No.1 does not
update (refresh) the data in the
END processing until the other
CPU modules receive the data.
The CPU module unit guarantee is
enabled:
(5) The CPU No.2 does not update
(refresh) the data in the END
processing until the CPU No.3 and
4 receive the data.
The CPU module unit guarantee is
enabled:
(9) All the CPU modules have
received the data, and the CPU
No.1 updates (refreshes) the data
in the END processing.
⇒ 1 → 101
(4) The CPU No.2
reflects (refreshes) the
data in the END
processing of the CPU
No.2.
(6) The CPU No.3 reflects
(refreshes) the data in the
END processing of the
CPU No.3.
(8) The CPU No.4 reflects
(refreshes) the data in the
END processing of the
CPU No.4.
The CPU module unit guarantee is
enabled:
(7) The CPU No.3 does not update
(refresh) the data in the END
processing until the CPU No.4
receives the data.
(1) The data is written from the program.
Scan time: 1ms
CPU No.2
CPU buffer memory
Scan time: 10ms
CPU No.3
CPU buffer memory
Scan time: 50ms
CPU No.4
CPU buffer memory
Scan time: 100ms