Mitsubishi Electric MELSEC iQ-R-R04CPU - Data Guarantee by Program

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16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
Data guarantee by program
This section describes how to avoid the inconsistency of data larger than 64 bits using the program. To set up the module-by-
module data guarantee using the parameters, use the multiple CPU setting. ( Page 304 Module-by-module data
guarantee)
Data guarantee in communication through the refresh
Inconsistency of transferred data can be avoided by setting the interlock device to a transfer number lower than the one for
the transferred data, because data is transferred in descending order from the highest setting number in the refresh settings.
Ex.
Interlock program in communication by refresh
• Parameter settings
• Program example
CPU No.1 refresh setting Direction CPU No.2 refresh setting
CPU
No.
Transfer
No.
Send/receive range for
each CPU module
Send/receive
device
setting
CPU
No.
Transfer
No.
Send/receive range for
each CPU module
Send/receive
device
setting
Number
of
points
start end start end Number
of
points
start end start end
CPU
No.1
Transfer
No.1
201M0M31 CPU
No.1
Transfer
No.1
201M0M31
Transfer
No.2
10 2 11 D0 D9 Transfer
No.2
10 2 11 D100 D109
CPU
No.2
Transfer
No.1
201M32M63 CPU
No.2
Transfer
No.1
201M32M63
M100 M0 M32
M0
M0
M0
M32
M32M32
SET M0
RST M0
RST M100
RST M32
SET M32
Write
instruction
Send program (CPU No.1) Receive program (CPU No.2)
Set send data
for D0 to D9.
Operation using receive
data (D0 to D9)