Mitsubishi Electric MELSEC iQ-R-R04CPU - Page 306

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16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
Prevention of data inconsistency by module-by-module data guarantee
The following table shows the preventive control against data inconsistency according to the presence or absence of module-
by-module data guarantee.
: With the preventive control against data inconsistency by the system, : Without the preventive control against data
inconsistency by the system
*1
*1 The countermeasure by the program is required. ( Page 312 Data guarantee by program)
*2 Limited to the case of access within the multiple CPU synchronous interrupt program (I45). ( Page 314 When accessing fixed scan
communication area)
Module-by-module data guarantee
Set up the module-by-module data guarantee.
[System Parameter]  [Multiple CPU Setting]  [Communication Setting between CPUs]  [PLC Unit Data]
Window
Displayed items
• For communications by the direct access with the CPU buffer memory other than the fixed scan
communication area, data is not guaranteed on a module-by-module basis even when this setting is
enabled, because the data on the CPU buffer memory of other CPU modules is directly read after execution
of the read instruction.
• Data send/receive timing coincides with an update interval of the CPU module with the slowest scan time,
because the next send/receive starts only after all CPU modules have completed data reception.
Communication method CPU buffer memory Fixed scan communication area
Module-by-module
data guarantee
enabled
Module-by-module
data guarantee
disabled
Module-by-module
data guarantee
enabled
Module-by-module
data guarantee
disabled
Communication through refresh 
Communication through direct access 
*2

Item Description Setting range Default
PLC Unit Data Specify whether data is guaranteed on a module-by-module
basis.
• Disable
• Enable
Disable