Motorola APX 3000 Detailed Service Manual

List of Figures xiii
List of Figures
Figure 2-1. DC Power Distribution........................................................................................................... 2-2
Figure 3-1. APX 3000 Overall Block Diagram ......................................................................................... 3-2
Figure 3-2. Transceiver (UHF1/ UHF2) Block Diagram (Power and Control Omitted) ............................ 3-3
Figure 3-3. Transceiver (VHF) Block Diagram (Power and Control Omitted) ......................................... 3-4
Figure 3-4. Transceiver (700/800 MHz) Block Diagram (Power and Control Omitted) ........................... 3-5
Figure 3-5. Receiver Block Diagram (UHF1)........................................................................................... 3-6
Figure 3-6. Receiver Block Diagram (UHF2)........................................................................................... 3-7
Figure 3-7. Receiver Block Diagram (VHF)............................................................................................. 3-7
Figure 3-8. Receiver Block Diagram (700/800 MHz)............................................................................... 3-7
Figure 3-9. Transmitter Block Diagram (UHF1/ UHF2) ........................................................................... 3-9
Figure 3-10. Transmitter Block Diagram (VHF)....................................................................................... 3-10
Figure 3-11. Transmitter Block Diagram (700/800 MHz)......................................................................... 3-10
Figure 3-12. Synthesizer Block Diagram (UHF1/ UHF2)......................................................................... 3-14
Figure 3-13. Synthesizer Block Diagram (VHF) ...................................................................................... 3-15
Figure 3-14. Synthesizer Block Diagram (700/800 MHz) ........................................................................ 3-15
Figure 3-15. Controller Interconnection Diagram .................................................................................... 3-21
Figure 3-16. Controller Electrical Overview............................................................................................. 3-23
Figure 3-17. Controller DC Block Diagram.............................................................................................. 3-24
Figure 3-18. V_SW_1.4 Switched Power Supply.................................................................................... 3-26
Figure 3-19. 5V Switched Power Supply................................................................................................. 3-27
Figure 3-20. Power-up Timing Regulators .............................................................................................. 3-28
Figure 3-21. Controller Clock Architecture .............................................................................................. 3-29
Figure 3-22. Overview of OMAP Interconnection with Controller Peripherals......................................... 3-30
Figure 3-23. OMAP Memory Interface .................................................................................................... 3-31
Figure 3-24. RX / TX SSI Configuration .................................................................................................. 3-32
Figure 3-25. Audio SSI Configuration...................................................................................................... 3-33
Figure 3-26. SPI and I2C Configuration .................................................................................................. 3-34
Figure 3-27. CPLD Block Diagram .......................................................................................................... 3-35
Figure 3-28. Audio TX Path Block Diagram ............................................................................................ 3-36
Figure 3-29. RX Audio Path Block Diagram ............................................................................................ 3-37
Figure 3-30. Control Top Block Diagram ................................................................................................. 3-38
Figure 3-31. GCAI Signal Configuration.................................................................................................. 3-39
Figure 3-32. GCAI Connector.................................................................................................................. 3-40
Figure 3-33. APX 3000 Encryption Architecture...................................................................................
... 3-42
Figure 3-34. GPS Block Diagram ............................................................................................................ 3-45
Figure 3-35. Accelerometer Block Diagram ............................................................................................ 3-46
Figure 3-36. Relation of Bluetooth & LF Antenna Assembly to Main Board............................................ 3-48
Figure 3-37. Bluetooth Connection Flowchart ......................................................................................... 3-49
Figure 3-38. Bluetooth/Controller Interface with Clock Sources.............................................................. 3-50
Figure 3-39. Bluetooth Functional Block Diagram................................................................................... 3-50
Figure 3-40. Bluetooth Low-Frequency Circuit Block Diagram ............................................................... 3-51
Figure 3-41. Bluetooth Low-Frequency Pairing Data Path...................................................................... 3-51
Figure 3-42. Detailed Low-Frequency Transmit/Receive Paths.............................................................. 3-52
Figure 3-43. Chip Power-Up/Power-Down Sequence (Exernal Input/Output Shown) ............................ 3-52
Figure 3-44. Current Distribution Tree for Bluetooth Circuitry ................................................................. 3-53
Figure 3-45. Bluetooth LF UART Connection Block Diagram ................................................................. 3-55
Figure 3-46. Bluetooth USB Interface To Main Board ............................................................................. 3-56
Figure 6-1. 32 kHz Clock Waveform ....................................................................................................... 6-2
Figure 6-2. 4 MHz Clock Waveform ........................................................................................................ 6-3
Figure 6-3. 12 MHz Clock Waveform ...................................................................................................... 6-4

Motorola APX 3000 Specifications

General

Brand	Motorola
Model	APX 3000
Category	Two-Way Radio
Language	English