Motorola MC68030 - Page 210

Bus Operation
7-64 MC68030 USER’S MANUAL MOTOROLA
not to be cached, CIIN must be asserted at the same time as STERM. The assertion of
CIIN
also has the effect of aborting the burst operation.
Figure 7-37. Burst Operation Flowchart — Four Long Words Transferred
END OF BURST
1) NEGATE AS AND DS
2) NEGATE DBEN
CONTROLLER
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) DRIVE R/W TO READ
3) DRIVE ADDRESS ON A31–A0
4) DRIVE FUNCTION ON FC2–FC0
5) DRIVE SIZE (SIZ1–SIZ0) (FOUR BYTES)
6) CACHE INHIBIT OUT (CIOUT) BECOMES
VALID
7) ASSERT ADDRESS STROBE (AS)
8) ASSERT CACHE BURST REQUEST (CBREQ)
9) ASSERT DATA STROBE (DS)
10) ASSERT DATA BUFFER ENABLE (DBEN)
1) SAMPLE CACHE INHIBIT IN (CIIN)
AND CACHE BURST ACKNOWLEDGE
(CBACK)
2) LATCH DATA
PRESENT DATA
1) DECODE ADDRESS
2) PLACE DATA ON D31-D0
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
4) ASSERT CACHE BURST ACKNOWLEDGE (CBACK)
TERMINATE CYCLE
1) REMOVE DATA FROM D31-D0
2) NEGATE STERM (IF NECESSARY)
3) NEGATE CBACK (IF NECESSARY)
EXTERNAL DEVICE
ADDRESS DEVICE
ACQUIRE DATA
WHEN 4 LONG WORDS TRANSFERRED UNTIL 4 LONG WORDS TRANSFERRED
START NEXT CYCLE