https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual 4/30
1,188 Kbits of fast block RAM () (*600 Kbits)
Six clock management tiles, each with phase-locked loop (PLL)
240 DSP slices (*120 DSPs)
Internal clock speeds exceeding 450 MHz ()
Dual-channel, 1 MSPS internal analog-digital converter (XADC)
Memory
128MiB DDR2
Serial Flash
microSD card slot
Power
Powered from USB or any 4.5V-5.5V external power source
USB and Ethernet
10/100 Ethernet PHY
USB-JTAG programming circuitry
USB-UART bridge
USB HID Host for mice, keyboards and memory sticks
Simple User Input/Output
16 Switches
16 LEDs
Two RGB LEDs
Two 4-digit 7-segment displays
Audio and Video
12-bit VGA output
PWM audio output
PDM microphone
Additional Sensors
3-axis accelerometer
Temperature sensor
Expansion Connectors
Pmod connector for XADC signals
Four Pmod connectors providing 32 total FPGA I/O
The Nexys A7 is compatible with Xilinx’s Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. Xilinx
offers free WebPACK™ versions of these toolsets, so designs can be implemented at no additional cost. The Nexys A7 is not supported by
the Digilent Adept Utility.
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