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Chapter 2 Analog Input
• AI Reference Trigger Signal*
• AI Pause Trigger Signal*
Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital
Input/Output and PFI, for more information.
Refer to the AI Convert Clock Signal Behavior For Analog Input Modules section for AI Convert
Clock signals and the cDAQ chassis.
AI Sample Clock Signal
A sample consists of one reading from each channel in the AI task. SampleClock signals the start
of a sample of all analog input channels in the task. SampleClock can be generated from external
or internal sources as shown in Figure 2-1.
Figure 2-1. AI Sample Clock Timing Options
Routing the Sample Clock to an Output Terminal
You can route SampleClock to any output PFI terminal. SampleClock is an active high pulse by
default.
AI Sample Clock Timebase Signal
The AI Sample Clock Timebase signal is divided down to provide a source for SampleClock.
SampleClockTimebase can be generated from external or internal sources.
SampleClockTimebase is not available as an output from the chassis.
AI Convert Clock Signal Behavior For Analog Input
Modules
Refer to the Scanned Modules, Simultaneous Sample-and-Hold Modules, Sigma-Delta Modules,
and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and
C Series I/O modules.
Programmable
Clock
Divider
AI Sample Clock
Timebase
PFI
Analog Comparison Event
Ctr n Internal Output
AI Sample Cloc
Sigma-Delta Module Internal Output
Analog Comparison
Event
20 MHz Timebase
80 MHz Timebase
PFI
100 kHz Timebase
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