After Sales
Technical Documentation
RAE/RAK–1N
PDA Hardware
Page 6 – 37
Original, 08/96
Main components
– E3G CPU
80386 based CPU. Static design. Using external clock source maximum
clock rate 33MHz. With internal PLL’s 23.96MHz. All needed peripherals
are integrated to the same chip. Peripherals are as follows:
– Two cascaded Interrupt Controllers (8259A), DOS compatible
– Three programmable Timer/Counters, 8254 standard
– DRAM bus controller, no external buffers or multiplexers needed
– Chip select unit
– Real time clock (RTC)
– Two 16550 UART’s with 16–byte FIFO’s
– IrDA signal conditioning and RS232/IrDA select
– LCD controller (640 x200 8 actual grey scales)
– Pulse Width Modulator Unit
– 8 x 10 keyboard scan unit
– System power management unit
– Expanded Memory Specification (EMS) Unit
– 32 KHz Oscillator with Phase Locked Loop circuits to generate all
needed frequencies
– JTAG (IEEE 1149.1) Boundary scan testing capability
E3G CPU is described in details in E3G EXTERNAL ARCHITECTURE
SPECIFICATION, Intel Corporation 5000 West Chandler Blvd. Chandler,
AZ 85226
– 1M*16bit FLASH memory 75 ns
– Intel 28F016SV 065
– 75 ns maximum read access time
– SMART voltage device with 5 Volt programming
– Used to store all program code
– 1 Million Erase Cycles Per Block
– Deep power down mode
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