NXP Semiconductors i.MX RT685 - DMIC

Table 9. Boot config (continued)
Boot mode ISP2 pin PIO1_17 ISP1 pin PIO1_16 ISP0 pin PIO1_15 Description
external Quad/Octal
SPI Flash device.
If there is no valid image
found, the RT6xx will
enter recovery boot or
ISP boot mode.
SDIO0 (eMMC) High Low Low
Boot from a eMMC
device connected to
SDIO 0 interface. The
RT6xx will look for a
valid image in the SD
card device. If there is
no valid image found,
the RT6xx will enter the
ISP boot mode based
on OTP
DEFAULT_ISP_MODE bits
(6:4, BOOT_CFG[0]).
— High Low High Reserved
Serial ISP (UART, SPI,
I
2
C, USB-HID)
High High Low
The Serial Interface
(UART, SPI, and I2C,
USB-HID) is used to
program OTP, external
Flash, SD or eMMC
device.
111 High High High
Serial Master boot (SPI
Slave, I
2
C Slave, or
UART, USB-HID) is
used to download a
boot image over the
serial interface (SPI
Slave, I
2
C Slave, or
UART, USB-HID)
For further details, please refer to RT6xx Non-Secure Boot ROM in RT6xx User Manual (document UM11147).
7.8 DMIC
MIMXRT685-EVK provides two DMIC interfaces described below.
7.8.1 On-board DMIC
The MIMXRT685-EVK incorporates a couple of DMICS on the board. Both DMICS share the data and clock signals and are
directly routed to the Port 2 of the MIMXRT685.
These pins are shared with the External DMIC. By default, on-board DMICS are selected (see R379 and R380).
For further details, refer to the board schematics.
NOTE
NXP Semiconductors
On-board peripherals
i.MX RT685 Evaluation Board, Rev. 0, March 20 2020
User's Guide 25 / 31