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General| Brand | NXP Semiconductors |
|---|---|
| Model | QorIQ LS1043ARDB |
| Category | Motherboard |
| Language | English |
Lists and describes acronyms and abbreviations used in the document.
Lists and describes additional documents for the LS1043ARDB.
Lists the features of the LS1043ARDB.
Shows the LS1043A processor block diagram.
Shows the LS1043ARDB top view.
Describes the LS1043ARDB's high-speed DRAM interface.
Details the integrated flash controller (IFC) interface features.
Details the Micron NOR flash memory on the board.
Details the Micron NAND flash memory on the board.
Describes main serial interfaces like RS-232, DSPI, eSDHC, and I2C.
Shows the LS1043ARDB universal asynchronous receiver/transmitter connections.
Describes the serial peripheral interface (SPI) connections on the LS1043ARDB.
Details the LS1043A processor's two Ethernet controllers.
Explains the Ethernet management interfaces (EMIs) and connected PHYs.
Describes the serializer/deserializer block and supported protocols.
Details Mini-PCIe card support, enabled by SerDes lanes.
Details the LS1043A processor's three integrated USB 3.0 controllers.
Describes the I2C bus connections and attached devices on the LS1043ARDB.
Shows the LS1043ARDB power supply block diagram.
Details the power ON and power sequencing activities.
Explains how the SW2 switch enables the 12V power supply for the board.
Describes the Complex Programmable Logic Device controller's role.
Lists the functions implemented by the CPLD controller.
Provides a detailed block diagram of the CPLD controller.
Details the CPLD registers and their memory map.
Shows a timing diagram of the power-on reset (POR) sequence.
Describes the reset configuration input signals on the LS1043ARDB.
Shows the LS1043ARDB reset architecture managed by the CPLD.
Details the voltage and current requirements for the DDR4 interface.
Explains how POVDD power line connects to specific pins.
Shows the LS1043ARDB clocking scheme.
Details how to select SYSCLK frequency based on switch settings.
Lists LS1043A MPIC assignments for interrupt sources.
Explains temperature measurement using thermal diode and monitor.
Shows the ARM/JTAG architecture.
Describes the MBED circuit as a serial and debug adapter.
Details GPIO functions, noting they are multiplexed and not dedicated.
Shows the memory map for CPLD registers.
Use this register to specify CPLD major version.
Use this register to specify CPLD minor version.
Use this register to specify printed circuit board assembly version.
Write this register to reset the whole system, maintaining CPLD registers.
Specify whether CPLD override physical switch is enabled.
Configure RCW source bits 0-7.
Configure RCW source bit 8.
Select flash bank.
Specify whether system clock has single-ended or differential input.
Specify output for UART1.
Specify input for SerDes PLL1 reference clock.
Select TDM clock or SDHC/USB.
Specify if status LED is ON or OFF.
Reset the whole system, initializing all CPLD registers to default values.
Indicate whether a TDM riser card is present on the LS1043ARDB.
Indicate if the RTC clock is assigned to RTC.
Control the EVDD voltage.
Enable CPLD register value override for SDHC_VS or SPI_CS0.
Select SDHC_VS or SPI_CS0.
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